ITR: Scalable Molecular Electronics

我们正在接近一个非常成功的计算时代的结束：摩尔定律统治的时代，每美元的处理能力每年翻一番。这一成功在很大程度上是基于互补金属氧化物半导体（CMOS）集成电路的进步。尽管我们已经开始期待并计划在日常生活中处理能力的指数级增长，但今天摩尔定律面临着迫在眉睫的挑战，这既来自深亚微米CMOS器件的物理特性，也来自芯片掩模和下一代制造工厂的巨大成本。化学组装电子纳米技术（CAEN）是目前正在研究的基于cmos的计算的一个有前途的替代方案。电子纳米技术（EN）利用量子力学效应，利用纳米级器件构建电子电路。CAEN的基本策略是用编译时间（便宜）代替制造精度（昂贵）。该研究将致力于将缺陷测量与计算机体系结构和编译器技术相结合，以从化学组装结构中创建电路。使用EN构建计算机系统需要对计算设备有新的思考方式；从电路到编译器无所不包。与传统的CMOS不同，CAEN不能用于构建复杂的结构。相反，人们制造密集的规则（但可能有缺陷）结构，我们称之为纳米织物，可以在制造后编程以实现复杂的电路。拟议的研究调查了如何通过开发新的电路技术、可重构计算、缺陷容限、架构抽象和创新的编译器技术来扩展CAEN，以创建每平方厘米10^10栅极当量以上的有用计算设备。虽然研究人员不会自己设计EN设备，但他们的目标是展示如何使用它们来创建计算设备，并指导EN科学家开发底层技术。研究人员将从四个层面来解决这个问题：逻辑构建模块：研究人员将开发EN器件模型和新的电路仿真技术，这些技术将允许预测功率、速度、密度、面积和延迟等重要指标的性能。这些模型将用于设计和确定用于计算系统的逻辑电路构建块（纳米块）的特性。制造：由于EN特别是CAEN制造的性质，器件将存在缺陷。研究人员将开发方法，使基于EN设备的系统能够在存在此类缺陷的情况下透明地工作。计算机体系结构：研究人员将开发一个抽象机器的层次结构，支持可重构计算并隐藏复杂性。分相抽象机（SAM）将程序划分为进程，这些进程将被映射到一个由二维网格上排列的瓦片组成的抽象机。每个tile将包含四个组件：一个有限状态机、一个数据路径段、一个本地内存和一个路由器。tile可以组合成一个完整的流水线数据路径。瓷砖本身将在纳米块中实现，这是纳米织物的基本单元。编译：将开发编译技术，将用通用编程语言（如C或Java）编写的程序映射到纳米结构。这项研究的重点是确保编译器可以扩展到纳米织物，它可以有数亿个组件。编译器根据控制流和内存访问模式将应用程序分解为一系列独立的sam。他们正在开发一种新的具有精确语义的中间表示，将所有控制流转换为数据流。IR统一了预测、推测和静态单一分配，并明确了数据流、控制流和同步。这极大地简化了许多优化，并为编译器的正式翻译和优化验证提供了框架。这项研究有潜力利用并指导电子纳米技术的发展，以低成本生产比传统CMOS电路密度高一百万倍的低功耗电路。

PROPOSAL ABSTRACTScalable Molecular Electronics We are approaching the end of a remarkably successful era in computing: The era where Moore's Law reigns, where processing power per dollar doubles every year. This success is based in large part on advances in complementary metal-oxide semiconductor (CMOS)-based integrated circuits. Although we have come to expect, and plan for, the exponential increase in processing power in our everyday lives, today Moore's Law faces imminent challenges both from the physics of deep-submicron CMOS devices and from the enormous costs of chip masks and next-generation fabrication plants. A promising alternative to CMOS-based computing being investigated is chemically assembled electronic nanotechnology (CAEN). Electronic nanotechnology (EN) constructs electronic circuits out of nanometer-scale devices that take advantage of quantum-mechanical effects. The fundamental strategy of CAEN is to substitute compilation time (which is inexpensive) for manufacturing precision (which is ex-pensive). The research will be directed at integrating defect measurements with computer architecture and compiler technology to create circuits from chemically assembled structures. Using EN to build computer systems requires new ways of thinking about computing devices; spanning everything from circuits to compilers. Unlike conventional CMOS, CAEN cannot be used to construct complex structures. Instead, one fabricates dense regular (but potentially defective) structures, which we call nanoFabrics, that can be programmed after fabrication to implement complex circuits. The proposed research investigates how to scale CAEN to create useful computational devices with more than 10^10 gate-equivalents per cm^2 by developing new circuit technology, reconfigurable computing, defect tolerance, architectural abstractions and innovative compiler technology While the researchers will not be designing the EN devices themselves, their goal is to show how they can be used to create computing devices and guide EN scientists in their development of the underlying technology. The investigators approach this problem at four levels: Logical Building Blocks: The researchers will develop models of EN devices and new circuit simulation technology that will allow predictions of performance across important metrics such as power, speed, density, area, and delay. These models will be used to design and determine the characteristics of logical circuit building blocks, nanoBlocks, for computing systems. Manufacturing: Due to the nature of EN and specifically CAEN fabrication, the devices will have defects. The investigators will develop methods which will allow systems based on EN devices to transparently work in the presence of such defects. Computer Architecture: The researchers will develop a hierarchy of abstract machines that support re-configurable computing and hide complexity. A split-phase abstract machine (SAM) will be used to partition programs into processes, which will be mapped to an abstract machine composed of tiles arranged on a 2-D grid. Each tile will contain four components: a finite state machine, a data path segment, a local memory, and a router. Tiles may be grouped together into a complete pipelined datapath. The tiles themselves will be implemented in nanoBlocks, the basic unit of the nanoFabric. Compilation: Compilation technology will be developed to map programs written in general-purpose programming languages, e.g. C or Java, to nanoFabrics. The research will focus on ensuring that the compiler will scale to nanoFabrics, which can have hundreds of millions of components. The compiler decomposes an application into a series of independent SAMs based on control flow and memory access patterns. They are developing a new intermediate representation with a precise semantics that turns all control flow into data flow. The IR unifies predication, speculation and static-single assignment and makes explicit data flow, control flow, and synchronization. This leads to an enormous simplification of many optimizations and provides the framework for formal translation and optimization validation of the compiler. This research has the potential to utilize, and guide the development of, electronic nanotechnology to inexpensively produce low-power circuits a million times more dense than conventional CMOS circuits.