Design Technologies for On-chip Networks

片上网络设计技术

• 批准号: 0305718
• 负责人: Bruce Wooley
• 金额: $ 37.5万
• 依托单位: Stanford University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-06-15 至 2007-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0305718&HistoricalAwards=false
• 关键词: Design; Technologies; chip; Networks

This research addresses design technologies for Systems on Chips andproposes a paradigm shift in their design, by focusing on a communication-centric approach that accepts and tolerates electrical-level errors within on-chip communication. The challenges of providing a fast, reliable and energy-efficient communication means on chip are addressed by designing SoCs as micro-networks of components and exploiting network technology to satisfy quality of service requirements (e.g., reliability, performance and energy bounds) under the limitation of unreliable signal transmission and non-negligible communication delays on wires.In particular, this research addresses the design of tools to support synthesis of control protocols for micro-networks, with particular emphasis on encoding (for error detection and correction), data packetization, switching and routing issues. The merits of the proposed research relate to demonstrating how networking techniques can solve on-chip communication problems, in view of the use of advanced fabrication technologies with large spread of physical parameters, unpredictable physical layouts and on-chip information traffic.

这项研究解决了片上系统的设计技术，并提出了一个范式转变，在他们的设计，通过专注于一个以通信为中心的方法，接受和容忍片上通信中的电子级错误。通过将SoC设计为组件的微网络并利用网络技术来满足服务质量要求（例如，可靠性，性能和能量边界）的限制下，不可靠的信号传输和不可忽略的通信延迟的wires.In特别是，本研究涉及的工具，以支持合成的控制协议的微型网络的设计，特别强调编码（错误检测和纠正），数据打包，交换和路由问题。所提出的研究的优点涉及到演示如何网络技术可以解决片上通信问题，鉴于使用先进的制造技术与大的传播的物理参数，不可预测的物理布局和片上信息流量。