Design Technologies for On-chip Networks

本研究解决了片上系统的设计技术，并提出了其设计的范式转变，通过关注以通信为中心的方法，在片上通信中接受和容忍电子级错误。通过将soc设计为组件的微网络，并利用网络技术在不可靠的信号传输和不可忽略的通信延迟的限制下满足服务质量要求（例如，可靠性，性能和能量界限），解决了在芯片上提供快速，可靠和节能通信手段的挑战。特别是，本研究解决了支持微网络控制协议综合的工具设计，特别强调编码（用于错误检测和纠正），数据分组，交换和路由问题。鉴于使用具有大量物理参数，不可预测的物理布局和片上信息流量的先进制造技术，所提出的研究的优点涉及展示网络技术如何解决片上通信问题。

This research addresses design technologies for Systems on Chips andproposes a paradigm shift in their design, by focusing on a communication-centric approach that accepts and tolerates electrical-level errors within on-chip communication. The challenges of providing a fast, reliable and energy-efficient communication means on chip are addressed by designing SoCs as micro-networks of components and exploiting network technology to satisfy quality of service requirements (e.g., reliability, performance and energy bounds) under the limitation of unreliable signal transmission and non-negligible communication delays on wires.In particular, this research addresses the design of tools to support synthesis of control protocols for micro-networks, with particular emphasis on encoding (for error detection and correction), data packetization, switching and routing issues. The merits of the proposed research relate to demonstrating how networking techniques can solve on-chip communication problems, in view of the use of advanced fabrication technologies with large spread of physical parameters, unpredictable physical layouts and on-chip information traffic.