Mapping Polygranular Parallel Processing to Shared, Heterogeneous, High-Performance Reconfigurable Computers

点击翻译按钮获取中文摘要

PetersonMapping Polygranular Parallel Programs (P3) to Shared, Heterogeneous, High Performance Reconfigurable Computers (HPRC)AbstractThe proposed project aims at the development of performance models and mapping algorithms as the theoretical foundation of a design infrastructure to support polygranular parallel programs executing on shared, heterogeneous, High Performance Reconfigurable Computers (HPRC). The project will develop a mathematical framework for characterizing the performance of polygranular parallel applications executing on HPRC systems. Moreover, the project will investigate computationally efficient approaches for optimally mapping applications to HPRC systems, providing dramatic improvement in design automation efficiency for HPRC and related computational platforms. Given the emergence of both embedded systems and the Grid as the basis for ubiquitous computing, the project will specifically address issues related to polygranular parallel application execution in a shared, heterogeneous environment.This project addresses the area of emerging computer systems architectures with the broader objective of providing the theoretic performance modeling and mapping infrastructure necessary to effectively exploit current and emerging hardware platforms with polygranular parallel programs. Hence, the program supports national efforts to meet next-generation computational needs with the grid and with embedded systems including system-on-chip. The computational capabilities of HPRC platforms promise significant performance and cost improvements for a spectrum of problem domains, such as image processing and graph algorithms.