ITR Collaborative Research: Programmable Graph Architecture for High Level Transformations of Multimedia Applications

用于多媒体应用高级转换的可编程图形体系结构摘要在本研究中，我们将研究可编程图形体系结构的转换算法、体系结构和设计，以将多媒体操作的高级表示直接映射到硬件中。我们预计，这种空间映射将大幅增加处理器芯片的计算密度，特别是对于那些广泛使用矩阵运算的计算。这些可编程图形体系结构上的计算将依赖于矩阵组和Cayley图之间的转换，而不是传统微处理器使用的传统算术和逻辑运算。特别是，我们计划：(I)为可编程图体系结构建立一个计算高效的多媒体应用程序指令集；(Ii)提供有效的算法来将这些指令转化为Cayley图中的图路由问题；以及(Iii)研究与Cayley图设计参数有关的优化问题。我们期望这项研究将导致下一代多媒体机器体系结构的原型可能与当今传统的细粒度微体系结构显著不同。由于多媒体在日常应用中的作用越来越大，设计和开发高效的多媒体处理器体系结构变得非常重要。

Programmable Graph Architectures For High Level Transformations ofMultimedia ApplicationsAbstractIn this research we will investigate transformational algorithms, architecture, and design of programmable graph architectures, to map high-level representations of multimedia operations directly into hardware. We expect that this spatial mapping will substantially increase the computational density of processor chips, especially for those computations that make extensive use of matrix operations. The computations on these programmable graph architectures will rely on transforms between matrix groups and Cayley graphs rather than traditional arithmetic and logic operations used by conventional microprocessors. In particular, we plan to: (i) establish an instruction set for programmable graph architectures that is computationally efficient for multimedia applications; (ii) provide efficient algorithms to transform these instructions to graph routing problems in Cayley graphs; and (iii) examine the optimization issues pertaining to the design parameters of Cayley graphs.We expect this investigation to lead to prototypes of next generation multimedia machine architectures that are likely to be significantly different from the conventional fine-grained microarchitectures of today. The design and development of efficient multimedia processor architectures is important due to the increasing role of multimedia in everyday applications.