Dependability Aspects in Configurable Embedded Operating Systems -- DanceOS

未来嵌入式系统的硬件设计将以可靠性降低为代价，展现出更多的并行性和能效。这给系统软件带来了新的挑战，尤其是操作系统（OS），它必须使用和提供软件措施来补偿不可靠的硬件。DanceOS项目通过资源高效的基于软件的容错技术的新颖组合来解决操作系统设计的这些挑战，这些技术可以通过面向方面的编程灵活地应用于操作系统和应用程序，由基于工具的（半）自动分析应用程序和操作系统代码驱动，导致后者在硬件容错方面严格面向问题的剪裁。第三个资助期的主要目标是(1)将我们的研究范围扩大到硬件/软件堆栈中操作系统的上下两层；(2)改进和优化我们的方法和工具，以更好地了解它们的基本局限性。在操作系统层之上，将特别关注分布式环境中的多线程服务。在操作系统下面，我们将非易失性存储器的体系结构视为必须解决的热门话题。这些系统为新的基于软件的容错措施和非常快速（可能是细粒度的）错误恢复机制提供了机会。另一方面，如果处理不当，非易失性存储器有将软错误转变为永久故障的风险。除了通过整合整个程序分析来优化面向方面的容错措施的资源效率之外，我们还计划探索一种基于代码生成的替代开发方法。结果将是一个高度可靠的（an编码的）类似osek的RTOS，与以前的工作相比，它将导致对使用通用方面语言进行基于软件的容错的基本限制的见解。我们的可靠性分析基础设施将被优化，以更快地产生结果，而对结果质量的影响很小。这将允许开发人员将我们的评估工具集成到开发周期中。贯穿大多数工作包的一个反复出现的主题是我们的故障模型的扩展。虽然主存和CPU寄存器中的单比特翻转在以前的项目阶段占主导地位，但我们现在的目标是将最新的研究成果纳入更现实的ISA和子ISA故障模型。

Future hardware designs for embedded systems will exhibit more parallelism and energy efficiency at the price of being less reliable. This bears new challenges for system software, especially the operating system (OS), which has to use and provide software measures to compensate for unreliable hardware. The DanceOS project addresses these challenges for OS design by a novel combination of resource-efficient software-based fault-tolerance techniques, which can flexibly be applied to the OS and the application by means of aspect-oriented programming, driven by a tool-based (semi-)automatic analysis of the application and OS code, resulting in a strictly problem-oriented tailoring of the latter with respect to hardware-fault tolerance.The main goals for the third funding period are (1) to broaden the scope of our research towards the layers above and below the OS in the hardware/software stack and (2) to refine and optimize our methods and tools to gain a better understanding of their fundamental limits.On top of the OS layer, a special focus will be on hardening multi-threaded services in distributed environments. Below the OS, we regard architectures with nonvolatile memories as a hot topic that must be addressed. These systems provide opportunities for novel software-based fault-tolerance measures and very fast (potentially fine-grained) error-recovery mechanisms. On the other hand, nonvolatile memories bear the risk of turning soft errors into permanent failure if not handled correctly.In addition to optimizing the resource efficiency of our aspect-oriented fault-tolerance measures by incorporating whole-program analysis, we plan to explorean alternative development approach based on code generation. The result will be a highly-dependable (AN-encoded) OSEK-like RTOS, which will -- by comparison to previous works -- lead to insights about fundamental limits of using general-purpose aspect languages for software-based fault tolerance. Our dependability analysis infrastructure will be optimized to yield results much faster with only very small compromises regarding result quality. This shall allow developers to integrate our assessment tools into the development cycle. A recurring topic throughout most work packages is the extension of our fault models. While single-bit flips in main memory and CPU registers were dominant in previous project phases, we now aim at incorporating recent research results on more realistic ISA- und sub-ISA fault models.