Collaborative Research: CRI-II (New) : A Digital/VLSI Test and Reliable Computing Research Laboratory
合作研究:CRI-II(新):数字/VLSI 测试和可靠计算研究实验室
基本信息
- 批准号:0958355
- 负责人:
- 金额:$ 2.31万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:2010
- 资助国家:美国
- 起止时间:2010-06-01 至 2014-05-31
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
Testing represents one of the major manufacturing costs in the semiconductor industry. Designing circuits with testability features significantly reduces testing costs and time. Thus, it is important for designers to be exposed to the concepts in testing which can help them design better and reliable products.In this collaborative project between the University of Toledo (UT) and Ohio Northern University (ONU), a "Digital/VLSI Test and Reliable Computing Research Laboratory" is being established for the development of computationally intensive algorithms and use of commercial CAD tools for testing digital, VLSI, and advanced semiconductor devices.Some of the research projects being carried out include: Novel Testing Techniques for Quantum Cellular Automata (QCA) circuits; Built In Self Test (BIST) for Embedded SRAMS in System on Chips; Testing Look-Up-Table (LUT) Delay Aliasing Faults in SRAM Based FPGAs Using Half-Frequencies; Analysis and Testing of Electromigration Failures; Testing and Modeling Soft Errors in FPGAs; Reliability Analysis and Device Failures in Advanced Semiconductor Devices; Reliability Issues Related to Power Consumption in VLSI Chips during Test; and Small Delay Defects and Test Generation.Educational modules developed from the research carried out in this project are integrated into a number of graduate and undergraduate courses at ONU and UT. Since applications of semiconductor chips are far and wide, many different industries including auto, aerospace, defense and healthcare may benefit from this project.
测试是半导体行业的主要制造成本之一。设计具有可测试性特征的电路显著降低了测试成本和时间。因此,重要的是让设计人员接触到测试的概念,这可以帮助他们设计更好和可靠的产品。在托莱多大学(UT)和俄亥俄州北方大学(ONU)之间的这个合作项目中,一个“数字/VLSI测试和可靠计算研究实验室”正在建立,用于开发计算密集型算法和使用商业CAD工具来测试数字,VLSI,目前正在进行的研究项目包括:量子元胞自动机(QCA)电路的新型测试技术;片上系统中嵌入式SRAM的内建自测试(BIST);使用半频率测试基于SRAM的FPGA的查找表(LUT)延迟混叠故障;电迁移故障的分析与测试; FPGA软错误的测试与建模;先进半导体器件的可靠性分析和器件故障;测试过程中与VLSI芯片功耗相关的可靠性问题;以及小延迟缺陷和测试生成。从该项目中进行的研究开发的教育模块被集成到ONU和UT的一些研究生和本科生课程中。由于半导体芯片的应用范围广泛,包括汽车、航空航天、国防和医疗保健在内的许多不同行业都可能从该项目中受益。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
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Srinivasa Vemuru其他文献
Effects of simultaneous switching noise on the tapered buffer design
同时开关噪声对锥形缓冲器设计的影响
- DOI:
- 发表时间:
1997 - 期刊:
- 影响因子:2.8
- 作者:
Srinivasa Vemuru - 通讯作者:
Srinivasa Vemuru
Srinivasa Vemuru的其他文献
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{{ truncateString('Srinivasa Vemuru', 18)}}的其他基金
EARS: Collaborative Research: Enhancing Spectral Access via Directional Spectrum Sensing Employing 3D Cone Filterbanks: Interdisciplinary Algorithms and Prototypes
EARS:协作研究:使用 3D 锥形滤波器组通过定向频谱传感增强频谱访问:跨学科算法和原型
- 批准号:
1247935 - 财政年份:2012
- 资助金额:
$ 2.31万 - 项目类别:
Standard Grant
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