EAGER: Integrating Chip Reliability in Designing Energy-Saving Scheduling Algorithms

能源消耗的大幅度增长给社会带来了许多严重的工程问题和经济问题。在过去的十年中，已经提出了许多节能调度算法来管理功耗。然而，节能算法对芯片寿命可靠性的影响（影响整体系统可持续性的重要因素）尚未得到计算机科学理论家的仔细研究。EAGER提案的目标是探索将芯片可靠性纳入设计的理论基础现代计算设施的节能调度算法。PI提出了一种新的模型，增强了现有的能量感知的处理器，通过强制执行额外的芯片寿命可靠性约束，这是建模为处理器频率变化的函数。新的排程演算法设计与分析技术被研究来解决这个问题，而专案的成果可能会转化为一系列相关的排程问题。除了研究所提出的理论问题，PI经验性地利用FreeBSD操作系统测量所开发算法的性能。本研究建议透过作业系统核心开发，将理论研究结果的实际意涵展现出来。

The substantial increase of energy consumption has brought up many serious engineering problems and economic concerns to our society. Many energy-saving scheduling algorithms have been proposed in the past decade to manage power consumption. However, energy-saving algorithms' impact on chip lifetime reliability, an important factor affecting overall system sustainability, has not been carefully examined by computer science theorists.The goal of this EAGER proposal is to explore the theoretical groundwork of incorporating chip reliability in designing energy efficient scheduling algorithms for modern computing facilities. The PI proposes a new model that augments the existing energy-aware schedulers by enforcing additional chip lifetime reliability constraints which are modeled as functions of processor frequency changes. Novel scheduling algorithm design and analysis techniques are investigated to solve this problem.The project outcome may potentially be transformative to a spectrum of related scheduling problems. In addition to studying the proposed theoretical problems, the PI empirically measures the performance of the developed algorithms by utilizing the FreeBSD operating system. This research suggests that through operating system kernel development, the practical implications of theoretical findings can be demonstrated.