EAGER: Integrating Chip Reliability in Designing Energy-Saving Scheduling Algorithms

点击翻译按钮获取中文摘要

The substantial increase of energy consumption has brought up many serious engineering problems and economic concerns to our society. Many energy-saving scheduling algorithms have been proposed in the past decade to manage power consumption. However, energy-saving algorithms' impact on chip lifetime reliability, an important factor affecting overall system sustainability, has not been carefully examined by computer science theorists.The goal of this EAGER proposal is to explore the theoretical groundwork of incorporating chip reliability in designing energy efficient scheduling algorithms for modern computing facilities. The PI proposes a new model that augments the existing energy-aware schedulers by enforcing additional chip lifetime reliability constraints which are modeled as functions of processor frequency changes. Novel scheduling algorithm design and analysis techniques are investigated to solve this problem.The project outcome may potentially be transformative to a spectrum of related scheduling problems. In addition to studying the proposed theoretical problems, the PI empirically measures the performance of the developed algorithms by utilizing the FreeBSD operating system. This research suggests that through operating system kernel development, the practical implications of theoretical findings can be demonstrated.