Collaborative Research: CCSS: Low-Complexity Wireless Sensor Architectures Based on Asynchronous Processing

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This collaborative research focuses on novel design principles for highly miniaturized low-complexity low-power wireless sensors and their analysis.In recent years integrated wireless sensors have emerged in a wide range of applications including health care, surveillance, smart buildings, disaster mitigation, and environment monitoring. However, new applications as implantable bio-potential sensors or submersible sensors for measuring mechanical stress require further miniaturization of existing state-of-the-art sensors hardware. As an additional challenge, these applications often require a significantly increased transmission data rate due to the need to perform multichannel sensing. Consequently, these approaches require the design of very low-power sensor hardware architectures, which can support reliable and secure transmission over these high-speed data links. Rather than studying the performance of traditional sensor architectures, signal processing techniques, and forward error correction (FEC) strategies for these challenging requirements, the goal of the proposed research is find and study novel low-complexity asynchronous communication and error correction strategies that are tailored to this emerging class of highly miniaturized low-power integrated wireless sensors. The results of this study have the potential to remove the power and throughput limitations given by traditional sensor hardware based on synchronous signal processing, and thus to enable significant advances in many sensing applications. In particular, the proposed research is able to provide a significant transformative impact on many other applications employing low-power modulation schemes, even outside the field of sensor systems. Another important aspect of the project is the education plan that combines the cross-disciplinary strengths of the PIs. This includes the integration of the research results into existing curricula, student exchanges, conference tutorials, and open access to all details of the proposed sensor architectures.The proposed project will significantly advance the state-of-the-art in integrated low-power low-complexity high-data-rate wireless sensor design by employing ideas from circuit design, signal processing, coding, and communication theory and practice in an interdisciplinary fashion. Specifically, a systematic solution for integrated wireless sensors will be developed by devising asynchronous delta modulation on the sensor interface in combination with asynchronous ultra wideband (UWB) transmission on the wireless radio interface in order to extensively decrease the power consumption of the sensor hardware. Further, to ensure that the sensor operates with guaranteed reliability over the noisy communication link, new non-binary FEC schemes with low complexity encoding are analyzed, whose data symbols consist of both asynchronous timing information and pulse signs. In particular, the project contributions are 1) to study design and properties of a novel asynchronous sensor signal interface based on a switched-capacitor amplitude sampling circuit; 2) to investigate the open problem of efficient FEC solutions for sensors based on asynchronous data modulation; and 3) to develop and analyze an asynchronous radio interface based on frequency shift keying on-off keying modulation for UWB data transmission.