SBIR Phase I: Novel Capacitor-less Dynamic Random Access Memory Technology with Energy Efficiency, Manufacturability, and Scalability

小型企业创新研究(SBIR)第一阶段项目的更广泛影响/商业潜力是颠覆价值350亿美元的动态随机存取存储器(DRAM)市场。DRAM是个人电脑、移动设备和其他电子产品的重要存储部件，目前还没有已知的替代品。该项目专注于将一种名为铁电DRAM(FEDRAM)的可制造、可扩展和超低功耗的替代产品商业化。由于其新颖的架构，FEDRAM将消除目前阻碍DRAM行业的许多障碍(即根据摩尔定律进行密度调整)。虽然许多新兴存储技术仍难以获得市场吸引力，但FEDRAM可以利用现有设施和设备制造；因此，它受益于相对较短的上市时间，并且与现有的DRAM相比具有成本竞争力。通过FEDRAM技术实现的移动设备将更轻、更时尚、更节能，而数据中心将实现显著的能源节约和芯片拥有成本。该小型企业创新研究(SBIR)第一阶段项目旨在通过实现几个关键目标来降低铁电动态随机存取存储器(FEDRAM)技术的风险。首先，该团队的目标是建立一个物理FEDRAM存储单元和阵列技术演示；第二个目标是设计和模拟刷新和纠错电路。具体地说，它将生产在存储器保持、功耗和读/写速度方面表现出有希望的特性的存储单元和阵列。基于这些结果，将设计和模拟具有相关刷新和纠错电路的更先进的阵列。第一阶段的结果将证明FEDRAM的功能如预期的那样，该材料可以集成到现有的制造设施中。实现这些目标将大大降低技术风险，并鼓励商业合作伙伴关系。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to disrupt the $35 billion Dynamic Random Access Memory (DRAM) market. DRAM - an essential memory component of PCs, mobile devices, and other electronics - has no known substitutes to date. This project focuses on commercializing a manufacturable, scalable, and ultra-low power replacement called Ferroelectric DRAM (FEDRAM). Due to its novel architecture, FEDRAM will unblock many of the obstacles that are currently hindering the DRAM industry (i.e. density scaling in accordance with Moore's Law). While it remains difficult for many emerging memory technologies to gain traction, FEDRAM can be manufactured using existing facilities and equipment; therefore, it benefits from a relatively short time-to-market, and is cost-competitive with existing DRAM. Mobile devices enabled by FEDRAM technology will be lighter, sleeker, and more energy-efficient, while data centers will realize significant savings in energy and cost of chip ownership.This Small Business Innovation Research (SBIR) Phase I project seeks to de-risk a Ferroelectric Dynamic Random Access Memory (FEDRAM) technology by accomplishing several key objectives. First, the team aims to build a physical FEDRAM memory cell and array technology demonstration; a secondary objective is to design and simulate refresh and error correction circuits. Specifically, it will produce memory cells and arrays that demonstrate promising characteristics in terms of memory retention, power consumption, and read/write speeds. Based on these results, more advanced arrays with the associated refresh and error correction circuitry will be designed and simulated. Phase I results will demonstrate that FEDRAM functions as predicted and that the material can be integrated in existing fabrication facilities. Completing these goals will significantly de-risk the technology and encourage commercial partnerships.