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SBIR Phase I: Novel Capacitor-less Dynamic Random Access Memory Technology with Energy Efficiency, Manufacturability, and Scalability

SBIR Phase I: Novel Capacitor-less Dynamic Random Access Memory Technology with Energy Efficiency, Manufacturability, and Scalability
SBIR 第一阶段:具有能源效率、可制造性和可扩展性的新型无电容器动态随机存取存储器技术
批准号:
1448305
负责人:
James Lin
金额:
$15.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2015
资助国家:
美国
项目状态:
已结题
起止时间:
2015-01-01 至 2015-12-31

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中文摘要
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英文摘要
The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to disrupt the $35 billion Dynamic Random Access Memory (DRAM) market. DRAM - an essential memory component of PCs, mobile devices, and other electronics - has no known substitutes to date. This project focuses on commercializing a manufacturable, scalable, and ultra-low power replacement called Ferroelectric DRAM (FEDRAM). Due to its novel architecture, FEDRAM will unblock many of the obstacles that are currently hindering the DRAM industry (i.e. density scaling in accordance with Moore's Law). While it remains difficult for many emerging memory technologies to gain traction, FEDRAM can be manufactured using existing facilities and equipment; therefore, it benefits from a relatively short time-to-market, and is cost-competitive with existing DRAM. Mobile devices enabled by FEDRAM technology will be lighter, sleeker, and more energy-efficient, while data centers will realize significant savings in energy and cost of chip ownership.This Small Business Innovation Research (SBIR) Phase I project seeks to de-risk a Ferroelectric Dynamic Random Access Memory (FEDRAM) technology by accomplishing several key objectives. First, the team aims to build a physical FEDRAM memory cell and array technology demonstration; a secondary objective is to design and simulate refresh and error correction circuits. Specifically, it will produce memory cells and arrays that demonstrate promising characteristics in terms of memory retention, power consumption, and read/write speeds. Based on these results, more advanced arrays with the associated refresh and error correction circuitry will be designed and simulated. Phase I results will demonstrate that FEDRAM functions as predicted and that the material can be integrated in existing fabrication facilities. Completing these goals will significantly de-risk the technology and encourage commercial partnerships.
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