FoMR: Collaborative Research: Single-Thread Multi-Accelerator Execution to Close the Dennard Scaling Gap

随着微处理器技术不断放缓的扩展趋势，传统的提高处理器性能的技术已经不再可行，要想获得更高的性能，需要一种截然不同的方法。该项目使用专门的加速器和代码注入技术开发多核芯片微体系结构，而不需要修改用户级软件、编译器和操作系统。这项研究的影响是帮助以新颖的方式指导微处理器设计，帮助维持性能改进，特别是在数据中心和大数据计算方面。该项目建立在最近一项前景看好的技术基础上，该技术涉及将程序阶段卸载到专门的处理器(加速器)上，这些处理器被调优以极高的效率执行具有特定特征(即并行性、控制依赖、内存行为)的程序。有两个主要挑战激励着这项工作的主要推动力。第一个问题是如何设计一个实用的系统来管理异类加速器的执行和动态翻译。第二个问题是如何设计一组加速器，使加速器的性能和能效比通用处理器的性能和能效提高一倍。这项工作通过设计分解的翻译子系统来解决第一个挑战，该分解的翻译子系统包括每个核的区域检测硬件、一组分解的编译器核和翻译缓存，以及基于动态代码属性和负载平衡将逻辑线程动态地重新映射到物理核的硬件/软件层。为了设计一组平衡的加速器，本工作分析程序以确定关键的程序行为，并为每个加速器开发目标加速器。最后，这包括综合时间资源分配算法的设计，该算法将共同优化缓存接口、一般核心属性和加速器执行模型的选择。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

With ever-slowing scaling trends in microprocessor technologies, traditional techniques of improving processor performance are no longer viable, and achieving higher performance requires a dramatically different approach. This project develops a multicore chip microarchitecture using specialized accelerators and code-injection techniques without needing to modify user-level software, compilers and operating systems. The impact of this research is to help steer microprocessor design in novel ways that can help sustain performance improvements, especially for datacenter and big-data computing. This project builds on a recent promising technique involves offloading program phases onto specialized processors (accelerators) which are tuned to execute programs with specific characteristics (i.e., parallelism, control dependence, memory behavior) at extremely high efficiency. There are two main challenges which motivate the major thrusts of this work. The first is the question of how to design a practical system for managing the execution of heterogeneous accelerators and dynamic translation. The second is how to design a set of accelerators which provide integer factors of improvement over general purpose processors' performance and energy efficiency. This work addresses the first challenge by designing a disaggregated translation subsystem, including region detection hardware at each core, a set of disaggregated compiler cores and a translation cache, and a hardware/software layer which dynamically re-maps logical threads to physical cores based on dynamic code properties and load balancing. To design a set of balanced accelerators, this work is analyzing programs to identify key program behaviors, and developing targeted accelerators for each. Finally, this includes the design of synthesis-time resource allocation algorithms which will co-optimize the choice of cache interface, general core attributes, and accelerator execution model.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.