SBIR Phase I: Security Evaluation Platform for Automating Inclusion of Hardware Security in Integrated Circuit Design

SBIR 第一阶段：自动将硬件安全纳入集成电路设计的安全评估平台

• 批准号: 2126885
• 负责人: Mahdi Orooji
• 金额: $ 25.6万
• 依托单位: SECURESEMI CORPORATION
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2021
• 资助国家: 美国
• 起止时间: 2021-11-15 至 2022-10-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2126885&HistoricalAwards=false
• 关键词: SBIR; Phase; Security; Evaluation; Platform

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to secure Integrated Circuit (IC) Intellectual Property (IP) against untrusted parties in the globalized IC supply chain. Outsourcing of IC foundries creates risks of IC reverse engineering, overproduction, theft, and even piracy. A promising method of achieving hardware IP security is by logically locking the functionality of a design by replacing a subset of the design components with programmable elements. The correct content of these elements forms the key for unlocking/activation of the design in a secure facility and/or via a secure protocol after manufacturing. A technical challenge in commercializing this technology is the long time period typically needed to assess the security of a locked design against state-of-the-art attack algorithms at the design phase. This project will address this technical challenge by developing an Artificial Intelligence (AI)-assisted design security analyzer tool to instantaneously provide an accurate attack runtime estimation on a locked design, significantly reducing the design time.This Small Business Innovation Research (SBIR) Phase I project will significantly shorten the time required to assess attack resiliency of an obfuscated (locked) Integrated Circuit (IC) design. Running the state-of-the-art Boolean Satisfiability solvers (SAT attack) on a state-of-the-art computer server to de-obfuscate a locked design can take time - ranging from days to months. Such a long security analysis time is prohibitive for deployment in the design process where iterative design optimizations are needed for making power, performance, area, and security (PPAS) trade-offs. This project aims to address this challenge by introducing a novel approach that will bring the security assessment time down to near zero using a machine-learning based model. Based on recent advancements in graph and geometric deep learning techniques, an innovative end-to-end security assessment framework is proposed that directly and losslessly ingests the original design as a graph-structured input, and then automatically learns the discriminative features that influence logic locking security. To support sufficient data for the proposed data-driven method, a logic locking macro-database will be developed that encompasses the required PPAS, attack and defense information.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

这个小型企业创新研究（SBIR）第一阶段项目的更广泛的影响/商业潜力是保护集成电路（IC）知识产权（IP）免受全球化IC供应链中不受信任方的侵害。 集成电路代工厂的外包带来了集成电路逆向工程、生产过剩、盗窃甚至盗版的风险。实现硬件IP安全的一种有前途的方法是通过用可编程元件替换设计组件的子集来逻辑地锁定设计的功能。这些元素的正确内容形成用于在安全设施中和/或在制造之后经由安全协议解锁/激活设计的密钥。将该技术商业化的一个技术挑战是在设计阶段评估锁定设计的安全性以对抗最先进的攻击算法通常需要很长的时间。该项目将通过开发人工智能（AI）辅助设计安全分析工具来应对这一技术挑战，该工具可以即时提供锁定设计的准确攻击运行时间估计，从而大大缩短设计时间。这个小型企业创新研究（SBIR）第一阶段项目将大大缩短评估混淆（锁定）集成电路（IC）设计的攻击弹性所需的时间。在最先进的计算机服务器上运行最先进的布尔可满足性求解器（SAT攻击）来对锁定的设计进行去模糊处理可能需要几天到几个月的时间。如此长的安全分析时间对于设计过程中的部署是禁止的，在设计过程中需要迭代设计优化以进行功率、性能、面积和安全（PPAS）权衡。该项目旨在通过引入一种新的方法来应对这一挑战，该方法将使用基于机器学习的模型将安全评估时间降低到接近零。基于图和几何深度学习技术的最新进展，提出了一种创新的端到端安全评估框架，该框架直接并丢失原始设计作为图结构输入，然后自动学习影响逻辑锁定安全性的判别特征。为了支持所提出的数据驱动方法的足够数据，将开发一个逻辑锁定宏数据库，其中包括所需的PPAS，攻击和防御信息。该奖项反映了NSF的法定使命，并已被认为是值得通过使用基金会的智力价值和更广泛的影响审查标准进行评估的支持。