SHF: Small: Holistic Design of High-performance and Energy-efficient Accelerators for Graph Neural Networks

图神经网络（gnn）已经成为下一代学习系统中最强大的技术之一，并在许多高影响力的领域受到关注，如图挖掘（图机、图聚类）、生物学（药物发现、疾病分类）、交通网络（流量预测）、推荐系统（用户项目预测、社会推荐）、电子商务分析、股市预测、自然语言处理（文本分类）、神经机器翻译)、图像处理（图像分类、对象检测、语义分割）和自主系统，等等。这些应用的爆炸式增长创造了对定制加速器设计的巨大需求，以满足GNN的计算需求，因为许多这些应用需要高通量和节能的GNN推理。传统的深度神经网络（DNN）加速器由于内存访问的不规则性、图结构带来的动态并行性以及学习算法中的密集计算等原因，无法有效地处理gnn。该项目通过架构研究、片上网络（NoC）设计、机器学习算法开发和算法架构协同优化等整体设计框架来解决这些挑战，旨在为gnn设计节能、高性能的加速器架构。该项目的跨领域性质将为GNN加速器设计中的许多关键问题提供有价值的见解和解决方案。这项研究还将通过将发现与教学和培训结合起来，在教育方面发挥重要作用。该项目的成果将通过技术出版物和演示文稿广泛传播给研究人员、工程师和教育工作者。该项目的目标是为各种基于图形的机器学习应用开发性能和能效大大提高的GNN加速器。为实现这一目标，本项目提出：(1)设计可变形的GNN加速器架构和可重构的NoC，以满足各种GNN的计算需求；(2)开发GNN加速器/算法协同优化探索框架，以最大化给定的基于图的机器学习任务的推理精度和性能（延迟、面积、能量等）；(3)为GNN加速器开发一个广泛的建模和仿真框架，用于验证所提出的设计方法；(4)使用现场可编程门阵列（fpga）实现所提出的加速器的小规模原型，并将其应用于现实世界的问题。这项及时的研究将极大地推进GNN加速的最新技术，使计算和机器学习社区受益，并对社会和整个美国计算行业的进步产生重大影响。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Graph Neural Networks (GNNs) have emerged as one of the most powerful techniques for next-generation learning systems, and are gaining attention in many high-impact domains such as graph mining (graph machine, graph clustering), biology (drug discovery, disease classification), traffic networks (traffic prediction), recommendation systems (user-item prediction, social recommendation), e-commerce analysis, stock market prediction, natural language processing (text classification, neural machine translation), image processing (image classification, object detection, semantic segmentation), and autonomous systems, among many others. The explosive growth of these applications has created an enormous demand for customized accelerator design to satisfy the computational requirements of GNNs, since many of these applications require high-throughput and energy-efficient GNN inference. Conventional deep neural network (DNN) accelerators cannot efficiently process GNNs due to the combination of irregular memory accesses, dynamic parallelism imposed by the graph structure, and the dense computation in learning algorithms. This project addresses these challenges with a holistic design framework spanning architecture study, Network-on-Chip (NoC) design, machine-learning algorithms development, and algorithm-architecture co-optimization with the aim of designing energy-efficient and high-performance accelerator architectures for GNNs. The cross-cutting nature of this project will offer valuable insights and solutions to many critical problems in GNN accelerator design. The research will also play a major role in education by integrating discovery with teaching and training. The outcomes of this project will be widely disseminated to researchers, engineers, and educators through technical publications and presentations. The goal of this project is to develop GNN accelerators with much-improved performance and energy efficiency for a wide variety of graph-based machine learning applications. To achieve this goal, this project proposes: (1) the design of a morphable GNN accelerator architecture and a reconfigurable NoC to satisfy the computational demands of various GNNs, (2) the development of a GNN accelerator/algorithm co-optimization exploration framework to maximize both inference accuracy and performance (latency, area, energy, etc.) for given graph-based machine learning tasks, (3) the development of an extensive modeling and simulation framework for GNN accelerators that will be used to validate the proposed design approach, and (4) the implementation of a small-scale prototype of the proposed accelerator using Field Programmable Gate Arrays (FPGAs) and its application to real-world problems. This timely research will greatly advance the state-of-the-art of GNN acceleration, benefit both the computing and machine-learning communities, and provide strong implications on advancements in society and the US computing industry-at-large.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.