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SBIR Phase I: Lightweight Learning-based Camera Image Signal Processing (ISP) for Photon-Limited Imaging

SBIR Phase I: Lightweight Learning-based Camera Image Signal Processing (ISP) for Photon-Limited Imaging
SBIR 第一阶段:用于光子限制成像的轻量级基于学习的相机图像信号处理 (ISP)
批准号:
2335309
负责人:
Preston Rahim
金额:
$27.47万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2024
资助国家:
美国
项目状态:
未结题
起止时间:
2024-03-01 至 2025-02-28

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英文摘要
The broader impact of this Small Business Innovation (SBIR) Phase I project will result from the ability to operate digital image sensors at lower light levels than is currently possible. The technology is expected to be deployable in any mid- to low-level camera device, with potential applications across all industries that leverage camera technology. Consumer applications that would benefit from improved low-light imaging include dashboard cameras and notebook cameras for videoconferencing; military and national security applications include night vision and autonomous navigation; while the technology will also enable improved diagnostic capabilities in medical procedures such as endoscopies. The technology is expected to have a direct impact on workforce development, and deployment of the solution will drive economics in consumer electronics.This Small Business Innovation Research (SBIR) Phase I project aims to achieve photon-limited image denoising using a lightweight algorithm that has the potential to be implemented on a camera chip. Accomplishing this goal requires several technological breakthroughs, collectively leading to a new image signal processor (ISP) known as a Small and Learnable ISP Module (SLIM). The key to SLIM is to identify the bottlenecks of physics-based ISPs and replace them with customized learning-based modules. Specifically, SLIM consists of five innovations: (i) learning-based frequency demodulation, (ii) guided denoising, (iii) learned feature extraction, (iv) learned indexing, and (v) learned filtering. In Phase 1, the team proposes to optimize SLIM and implement it on a field programmable gate array (FPGA). This includes shrinking the size of the filters and streamlining the indexing scheme to further speed up SLIM, introducing new encoders to improve generalization, and optimizing the memory, communication, and processing through improved programming and real-data evaluation and demonstration.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
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  • 资助金额:
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