Implementation of Fast, Low Latency 2D IIR Digital filters using Separate Computation of Semizero-State and Zero-Input Responses.

本文讨论了使用块处理的快速、低延迟2D数字滤波器的多处理器实现。将二维数据平面划分为正方形区域，采用环形连接的多处理器系统进行垂直方向的区域间并行处理，每个处理器对每个区域进行过滤。垂直状态变量从处理器传输到处理器。在特定区域内，将下边缘垂直状态变量置零，由左边缘水平状态变量和输入数据样本计算状态变量的半状态响应，然后计算该区域上、右边缘状态变量的完全响应和该区域的滤波输出。将计算出的垂直状态变量从一个处理器传送到下一个上位处理器。加工在垂直方向上进行，一步一个区域。与传统的块处理算法相比，该算法的计算量显著减少。该系统具有较高的吞吐量和较低的时延。首先，对用单位状态方程表示的滤波器进行处理。还执行了区域间并行处理。计算负载被平均分配给每个处理器，因此系统以高效率工作。该系统采用TI公司的C-40信号处理器模拟器构建。其次，对由级联低阶段组成的滤波器进行处理。与前者相比，该系统具有更低的运算量和更高的可实现吞吐量。并用C-40模拟器进行了仿真验证。

This paper treats multiprocessor implementation of fast, low latency 2D digital filters using block processing. 2D data plane is partitioned into square regions and a ring connected multiprocessor system is used for inter-region parallel processing in vertical direction, each processor filtering each region. Vertical state variables are transfered from a processor to a processor. In a particular region, putting the bottom edge vertical state variables to be zeroes, semizerostate responses of state variables by the left edge horizontal state variables and the input data samples are computed, then complete responses of state variables at the upper and right edges and filter outputs of the region are computed. Computed vertical state variables are transferred from a processor to the next upper processor. The processing progresses in vertical direction, one region at one step. The algorithm results significant decrease in computation amount compared to the conventional block processing algorithm. The system can give high throughput and low latency.First, the filters expressed by an unity state equation are treated. Inter-region parallel processing is also performed. Computation is load equally allotted to each processor so that the system works in high efficiency. The system was constructed with TI's C-40 signal processor simulator.Secondly, the filters consisting of cascaded low-order sections are treated. the system has lower computation amount and higher achievable throughput than the former. These are confirmed by simulation using C-40 simulator.