An ultra-low-power, modular PSSS-FEC-ARQ combined processor for 100 Gbps wirelesscommunication in the THz-band

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Although 100 Gbps communication has been demonstrated recently, it still consumes too much hardware resources and energy for mobile devices. Thus, there is a need for low complexity algorithms that can be employed for 5G and beyond approaches. On one hand, the various algorithms used for the processing of data have to be lightweight, in order to lead to transceivers realizable with acceptable power consumption. On the other hand, the implementation has to be powerful to mitigate limitations of the analog frontend that operates in extremely demanding conditions. This project proposes the investigation of a modular architecture for 100 Gbps wireless communication with the main focus on power and energy efficiency. Combining the baseband processing with forward error correction and automatic repeat request should allow us to use energy much more efficiently. Moreover, the investigation of modular baseband processing should allow following user demands according data rates much closer than peak-rate oriented processing. This again has high impact on dynamic power consumption. We do not propose to build the individual processing elements of the >100 Gbps system, instead, we propose a research on the demanding cross-layer optimizations and modular architectures for high-speed mobile transceivers. The main target is reducing power consumption as much as possible but below 0.5 W @ 100 Gbps (which results in 0.5 pW/b) for the combined baseband and error handling entities (ARQ, FEC). Beyond the immediate visible results of the project this research will generate new ideas of optimal combination of signal processing components in communication chains. Moreover, it will lead to new insight into massive ultra-low power systems by using different concepts of modularity, multi-core processing and algorithmic chaining.