An ultra-low-power, modular PSSS-FEC-ARQ combined processor for 100 Gbps wirelesscommunication in the THz-band

用于太赫兹频段 100 Gbps 无线通信的超低功耗模块化 PSSS-FEC-ARQ 组合处理器

• 批准号: 442607813
• 负责人: Dr.-Ing. Lukasz Lopacinski
• 金额: --
• 依托单位: Leibniz-Institut für innovative Mikroelektronik (IHP GmbH)
• 依托单位国家: 德国
• 项目类别: Independent Junior Research Groups
• 资助国家: 德国
• 项目状态: 未结题
• 来源: https://gepris.dfg.de/gepris/projekt/442607813?language=en
• 关键词: ultra; low; power; modular; PSSS

Although 100 Gbps communication has been demonstrated recently, it still consumes too much hardware resources and energy for mobile devices. Thus, there is a need for low complexity algorithms that can be employed for 5G and beyond approaches. On one hand, the various algorithms used for the processing of data have to be lightweight, in order to lead to transceivers realizable with acceptable power consumption. On the other hand, the implementation has to be powerful to mitigate limitations of the analog frontend that operates in extremely demanding conditions. This project proposes the investigation of a modular architecture for 100 Gbps wireless communication with the main focus on power and energy efficiency. Combining the baseband processing with forward error correction and automatic repeat request should allow us to use energy much more efficiently. Moreover, the investigation of modular baseband processing should allow following user demands according data rates much closer than peak-rate oriented processing. This again has high impact on dynamic power consumption. We do not propose to build the individual processing elements of the >100 Gbps system, instead, we propose a research on the demanding cross-layer optimizations and modular architectures for high-speed mobile transceivers. The main target is reducing power consumption as much as possible but below 0.5 W @ 100 Gbps (which results in 0.5 pW/b) for the combined baseband and error handling entities (ARQ, FEC). Beyond the immediate visible results of the project this research will generate new ideas of optimal combination of signal processing components in communication chains. Moreover, it will lead to new insight into massive ultra-low power systems by using different concepts of modularity, multi-core processing and algorithmic chaining.

尽管最近已经演示了100 Gbps通信，但对于移动的设备来说，它仍然消耗太多的硬件资源和能量。因此，需要可以用于5G和超越方法的低复杂度算法。一方面，用于数据处理的各种算法必须是轻量级的，以便导致收发器以可接受的功耗实现。另一方面，实现必须强大，以减轻在极端苛刻条件下运行的模拟前端的限制。该项目提出了一种用于100 Gbps无线通信的模块化架构的研究，主要关注功率和能源效率。将基带处理与前向纠错和自动重传请求相结合，应该可以让我们更有效地使用能量。此外，模块化基带处理的研究应该允许根据比面向峰值速率的处理更接近的数据速率来遵循用户需求。这再次对动态功耗产生很大影响。我们不建议构建>100 Gbps系统的单个处理元件，相反，我们建议研究高速移动的收发器的跨层优化和模块化架构。主要目标是尽可能降低功耗，但低于0.5 W@100 Gbps（这导致0.5 pW/B）的组合基带和错误处理实体（ARQ，FEC）。除了该项目的直接可见结果之外，这项研究还将产生通信链中信号处理组件优化组合的新想法。此外，通过使用模块化、多核处理和算法链的不同概念，它将导致对大规模超低功耗系统的新见解。