Construction of Multi-Valued Picture Processing System
Construction of Multi-Valued Picture Processing System
批准号:
06650447
负责人:
IMANISHI Shigeru
金额:
$1.28万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for General Scientific Research (C)
财政年份:
1994
资助国家:
日本
项目状态:
已结题
起止时间:
1994 至 1995
中文摘要
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英文摘要
Becase the gray and colored images have multiple levels, a multiple-valued logic system for picture processing is more effective as compared with a binary logic system.We propese several operations and report ternary digital picture processing sircuits (TDPPC's). The TDPPC's consist of ternary/binary level converters, binary/ternary level converters, ternary comparators, neighborhood operation circuits, ternary half adders and center pixel output circuit. Algorithms for noise reduction, border line extraction, logic difference, thinning, and connected component extraction on ternary logic are used in the developments and designs of the TDPPC's. Moreover, we construct a basic system including a host personal computer. TDPPC's utilized in this system are verified by the algorithms.Further, we examine border extraction with Laplatian-Gaussian filter by ternary method, extracting image contours for full color image by using multi-valued processing with Hue・Saturation・Light (HSL), and improvement of printing for digital picture. In extracting region system, becase the histogram processing can be adapted for hue and saturation in addition to light, we used a multiple-valued output system combined hue and light, or hue and saturation. Therefore, we examine to extract the appropriate state of original picture at once.Moreover, we examine ternary fundamental operation circuits which are compositions for circuits, and realized ternary picture processing circuits in voltage-mode. And we examine bidirectional current-mode circuits. Those ternary picture processing circuits are expected speeding up by paraller processing. The results have been published in papers and conferences.
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H.Yamada, N.Muranaka and S.Imanishi: "A Color Image Processing with Laplatian-Gaussian Filter by Ternary Method" IEICE Japan, Second Class Society for the Study. MVL96-7. 47-54 (1996)
H.Yamada、N.Muranaka 和 S.Imanishi:“采用三元方法的拉普拉高斯滤波器的彩色图像处理”IEICE 日本,二级研究学会。
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村中徳明,今西茂: "3値画像処理回路の構成" 電気学会論文誌C(電子・情報・システム部門誌). 115-C(3月号予定). (1995)
Noriaki Muranaka,Shigeru Imanishi:“三态图像处理电路的配置”,日本电气工程师协会学报 C(电子、信息和系统部门期刊)115-C(预定 1995 年 3 月号)。
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吉岡,武,村中,徳明,今西,茂: "5値3進SD数双方向電流モード加算器の構成" 電気学会論文誌C(電子・情報・システム部門誌). 115-C. 1252-1258 (1995)
Yoshioka、Takeshi、Muranaka、Noriaki、Imanishi、Shigeru:“五值三进制 SD 数双向电流模式加法器的配置”日本电气工程师学会汇刊 C(电子、信息和系统部门期刊)115-C。 1252-1258(1995)
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木村,雅樹,村中,徳明,今西,茂: "多値方式を用いたフルカラー画像の色相・彩度・明度(HSL)による画像輪郭抽出" 多値論理研究会,多値論理研究ノート. 18. 7.1-7.8 (1995)
Kimura、Masaki、Muranaka、Noriaki、Imanishi、Shigeru:“使用多值方法基于全色图像的色调、饱和度和亮度 (HSL) 的图像轮廓提取”多值逻辑研究小组,多值逻辑研究笔记 18 .7.1-。 7.8(1995)
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吉岡武,村中徳明,今西茂: "p値r進SD数双方向電流モード加算器の構成" 電子情報通信学会,第二種研究会,多値技報. MVL95. 46-52 (1995)
Takeshi Yoshioka、Noriaki Muranaka 和 Shigeru Imanishi:“p 值 r-adic SD 数双向电流模式加法器的配置”,电子、信息和通信工程师学会,2 类研究组,多值 MVL95(多值技术报告)。 1995)
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共 19 条
Molecular based analyzes of distantly related interspecific and intergeneric hybrids (including somatic hybrids) for useful gene cloning
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批准号:07660004
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项目类别:Grant-in-Aid for Scientific Research (C)
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资助金额:$1.22万
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财政年份:1995
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负责人:IMANISHI Shigeru
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依托单位: