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Parallel Computer System -Harray-

Parallel Computer System -Harray-
并行计算机系统-Harray-
批准号:
63550280
负责人:
MURAOKA Yoichi
金额:
$1.47万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for General Scientific Research (C)
财政年份:
1988
资助国家:
日本
项目状态:
已结题
起止时间:
1988 至 1989

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项目成果

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中文摘要
翻译
并行处理系统--Harray--是一个由1000个处理器组成的多处理器系统,旨在快速执行科学计算。因为科学和工程程序都是用FORTRAN语言编写的,所以-Harray-系统的目标是快速执行FORTRAN程序.因为FORTRAN是一种顺序编程语言,所以由编译器来揭示顺序编写的程序中的并行性。然而,顺序语言和并行执行之间的语义差距非常大。因此,该系统采用了“受控数据流”机制来弥合这一语义鸿沟,并充分利用了控制流和数据流机制。在受控数据流机制中,一个FORTRAN程序被分成一组宏块,宏块是一组语句,其中只有一个控制依赖入口点。宏块是其执行由受控数据流机制控制的单元。宏块中的操作由流水机制执行,宏块的执行顺序由受控流机制控制。在本报告所述期间,完成了一个处理单元的电路设计和系统设计。
英文摘要
The parallel processing system -Harray- is a multiprocessor system consisting of one thousand processors aiming at fast execution of scientific computations. The -Harray- system targets fast execution of FORTRAN programs because scientific and engineering programs have been written in FORTRAN. Because FORTRAN is a sequential programming language, it is up to a compiler to expose parallelism in sequentially written programs. However, the semantic gap between a sequential language and parallel execution is very wide. Therefore, the -Harray- system adopts a "Controlled Dataflow" mechanism to bridge this semantic gap and take full advantage of both the control flow and the dataflow mechanism. In the Controlled Dataflow mechanism, a FORTRAN program is devided into a set of macro-blocks, which is a set of statements, including only one entry point of control dependency. A macro-block is a unit whose execution is controlled by the Controlled Dataflow mechanism. Operations in a macro-block are executed by the dataflow mechanism, while the execution order of macro-block is controlled by the controlled flow mechanism.In the period reported in this report, the circuit design as well as the system design of a processing element have been completed.
期刊论文(26)
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科研奖励(0)
会议论文
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作者: []
通讯作者:
Y, Muraoka: "Highly Parallel Processing System" Journal of IEICE, Vol.7, pp.733-741 (1989.7).
Y,Muraoka:“高度并行处理系统”IEICE 杂志,第 7 卷,第 733-741 页(1989.7)。
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通讯作者:
山名早人,他: "A Preceding Activation Scheme with Graph Unfolding for the Parallel Processing System-Harray-" Proc.of Supercomputing '89. 1989. 108-119 (1989)
Hayato Yamana 等人:“并行处理系统的图展开的前序激活方案 - Harray -”Proc. of Supercomputing 89。108-119 (1989)
DOI: --
发表时间:
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作者: []
通讯作者:
T.Marushima et al.: "Loop processing Mechanism doalong, Transaction of IEICE" J71-D, pp.1511-1517 (1988.7).
T.Marushima 等人:“循环处理机制 doalong,IEICE 交易”J71-D,第 1511-1517 页(1988.7)。
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通讯作者:
26
    j-GRID
    • 批准号:
      12558031
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $8.45万
    • 财政年份:
      2000
    • 负责人:
      MURAOKA Yoichi
    • 依托单位:
    Thread Migration System for Distributed Computing
    • 批准号:
      11680372
    • 项目类别:
      Grant-in-Aid for Scientific Research (C)
    • 资助金额:
      $2.05万
    • 财政年份:
      1999
    • 负责人:
      MURAOKA Yoichi
    • 依托单位:
    Research on Scalable High Quality Wide Area ATM Network
    • 批准号:
      07558041
    • 项目类别:
      Grant-in-Aid for Scientific Research (A)
    • 资助金额:
      $9.6万
    • 财政年份:
      1995
    • 负责人:
      MURAOKA Yoichi
    • 依托单位:
    Internet Distributed Database
    • 批准号:
      06452395
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $3.97万
    • 财政年份:
      1994
    • 负责人:
      MURAOKA Yoichi
    • 依托单位:
    海外基金