Parallel Computer System -Harray-

并行计算机系统-Harray-

• 批准号: 63550280
• 负责人: MURAOKA Yoichi
• 金额: $ 1.47万
• 依托单位: Waseda University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for General Scientific Research (C)
• 财政年份: 1988
• 资助国家: 日本
• 起止时间: 1988 至 1989
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-63550280/
• 关键词: Parallel Processing; Data Flow; FORTRAN; スーパーコンピュータ; データフロー

The parallel processing system -Harray- is a multiprocessor system consisting of one thousand processors aiming at fast execution of scientific computations. The -Harray- system targets fast execution of FORTRAN programs because scientific and engineering programs have been written in FORTRAN. Because FORTRAN is a sequential programming language, it is up to a compiler to expose parallelism in sequentially written programs. However, the semantic gap between a sequential language and parallel execution is very wide. Therefore, the -Harray- system adopts a "Controlled Dataflow" mechanism to bridge this semantic gap and take full advantage of both the control flow and the dataflow mechanism. In the Controlled Dataflow mechanism, a FORTRAN program is devided into a set of macro-blocks, which is a set of statements, including only one entry point of control dependency. A macro-block is a unit whose execution is controlled by the Controlled Dataflow mechanism. Operations in a macro-block are executed by the dataflow mechanism, while the execution order of macro-block is controlled by the controlled flow mechanism.In the period reported in this report, the circuit design as well as the system design of a processing element have been completed.

并行处理系统Harray是一个由1000个处理器组成的多处理器系统，旨在快速执行科学计算。-Harray系统的目标是快速执行FORTRAN程序，因为科学和工程程序都是用FORTRAN编写的。因为FORTRAN是一种顺序编程语言，所以在顺序编写的程序中暴露并行性是由编译器决定的。然而，顺序语言和并行执行之间的语义差距非常大。因此，-Harray-System采用了受控数据流机制来弥合这种语义鸿沟，并充分利用了控制流和数据流机制。在受控数据流机制中，FORTRAN程序被分成一组宏块，这是一组语句，只包括一个控制依赖的入口点。宏块是其执行由受控数据流机制控制的单元。宏块中的操作由数据流机制执行，宏块的执行顺序由受控流机制控制，在本报告所述期间，已经完成了处理单元的电路设计和系统设计。

项目成果

H.Yamana et al.: "System Architecture of Parallel Processing System -Harray-" Proc. of 1988 International Conference on Supercomputing, pp.76-89 (1988).

H.Yamana 等人：“并行处理系统的系统架构 -Harray-”Proc。

Y, Muraoka: "Highly Parallel Processing System" Journal of IEICE, Vol.7, pp.733-741 (1989.7).

Y，Muraoka：“高度并行处理系统”IEICE 杂志，第 7 卷，第 733-741 页（1989.7）。

山名早人,他: "A Preceding Activation Scheme with Graph Unfolding for the Parallel Processing System-Harray-" Proc.of Supercomputing '89. 1989. 108-119 (1989)

Hayato Yamana 等人：“并行处理系统的图展开的前序激活方案 - Harray -”Proc. of Supercomputing 89。108-119 (1989)

T.Marushima et al.: "Loop processing Mechanism doalong, Transaction of IEICE" J71-D, pp.1511-1517 (1988.7).

T.Marushima 等人：“循环处理机制 doalong，IEICE 交易”J71-D，第 1511-1517 页（1988.7）。

萩原孝: bit. 4、21. 443-454 (1989)

萩原隆：位 4, 21. 443-454 (1989)