Hardware implementation of trellis-coded co-channel interference canceller for microcelluar radio

微蜂窝无线电网格编码同信道干扰消除器的硬件实现

• 批准号: 08555091
• 负责人: YOSHIDA Susumu
• 金额: $ 7.36万
• 依托单位: KYOTO UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (A)
• 财政年份: 1996
• 资助国家: 日本
• 起止时间: 1996 至 1997
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-08555091/
• 关键词: mobile radio; fading channel; co-channel interference; interference canceller; hardware inplementation; PLD; laboratory experiment; トレリス符号化変調; マイクロセル; 信号処理

In order to realize high speed transmission in digital mobile communications, the design trials of equalizers and co-channel interference cancellers are being investigated actively. Nonlinear co-channel interference canceller which uses path diversity has been proved to be an effective method against multipath propagation causing frequency selective fading in high speed transmission. The trellis-coded co-channel interference canceller (TCC) is well-known to yield a superior path diversity effect and co-channel interference cancelling capability, but the computational complexity increases rapidly when the multipath delay becomes large. In this research, by reducing the computational bits in the circuit, and simplifying the calculation complexity without sacrificing the performance, we successfully designed a small-scale, high speed adaptive TCC.This TCC is realized on a FPGA circuit. Its operation and processing speed have been confirmed to be consistent with the design goal.

为了在数字移动的通信中实现高速传输，均衡器和同频干扰消除器的设计试验正在积极进行。利用路径分集技术的非线性同信道干扰消除器是一种有效的抗多径传播引起的频率选择性衰落的方法。网格编码的同信道干扰消除器（TCC）具有上级的路径分集效果和同信道干扰消除能力，但当多径时延变大时，计算复杂度迅速增加。在本研究中，我们通过减少电路中的运算位数，在不牺牲性能的前提下简化运算复杂度，成功地设计了一种小规模、高速的自适应TCC，并在FPGA电路上实现。其运行和处理速度已被证实是符合设计目标。

项目成果

H.Murata and S.Yoshida: "Joint frequency offset and delay profile estimation technique for maximum-likelihood sequence estimation" Proc.of 1st IEEE International Conference on Information, Communications & Signal Processing (ICICS'97). 1327-1330 (1997)

H.Murata 和 S.Yoshida：“用于最大似然序列估计的联合频率偏移和延迟分布估计技术”Proc.of 第一届 IEEE 国际信息、通信会议

北川 恵一: "FPGAを用いた2Mbps実時間処理可能な適応MLSEの試作" 電子情報通信学会技術研究報告. RCS97-83. 15-20 (1997)

Keiichi Kitakawa：“使用 FPGA 进行 2Mbps 实时处理的自适应 MLSE 原型”IEICE 技术研究报告 15-20 (1997)。

H.Murata: "Joint frequency offset and delay profile estimation technique for maximum-likelihood sequence estimation" Proc.of 1st IEEE International Conference on Information,Communications & Signal Processing(ICICS'97). 1327-1330 (1997)

H.Murata：“用于最大似然序列估计的联合频率偏移和延迟分布估计技术”Proc.of 1st IEEE International Conference on Information,Communications

H.Murata: "Trellis-coded co-channel interference canceller with interleaving" to be published in IEICE Trans.Commun.(1998)

H.Murata：“Trellis-coded co-channel Interleaving 干扰消除器”将在 IEICE Trans.Commun. 上发表（1998）

H.Murata: "Trellis-coded co-channel interference canceller with interleaving" to be published in IENCE Trans.Commun.(1998)

H.Murata：“带有交错的网格编码同信道干扰消除器”将在 IENCE Trans.Commun 上发表。(1998)