Formal Verification of Quantum Logic Circuits

量子逻辑电路的形式验证

• 批准号: DP220102059
• 负责人: Prof Yuan Feng
• 金额: $ 31.33万
• 依托单位: University of Technology Sydney
• 依托单位国家: 澳大利亚
• 项目类别: Discovery Projects
• 财政年份: 2022
• 资助国家: 澳大利亚
• 起止时间: 2022-12-31 至 2025-12-30
• 项目状态: 未结题
• 来源: https://dataportal.arc.gov.au/RGS/Web/Grants/DP220102059
• 关键词: Formal; Verification; Quantum; Logic; Circuits

The project aims to develop comprehensive theory and effective techniques for formal modelling, equivalence checking, and model checking of quantum circuits. The research is timely as the rapid growth of quantum computing hardware makes it an urgent task to develop verification techniques for quantum hardware design and quantum compilers. The successful development of the algorithms and software tools proposed in this project will significantly advance the knowledge on formal verification of quantum circuits and help Australian quantum start-ups build and maintain an internationally leading position in the rapidly emerging quantum electronic design automation (EDA) industry.

该项目旨在为量子电路的形式化建模、等价性检验和模型检验开发全面的理论和有效的技术。这项研究是及时的，因为量子计算硬件的快速增长使得开发量子硬件设计和量子编译器的验证技术成为一项紧迫的任务。该项目中提出的算法和软件工具的成功开发将大大推进量子电路形式验证的知识，并帮助澳大利亚量子初创企业在迅速崛起的量子电子设计自动化（EDA）行业中建立和保持国际领先地位。