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RESERCH ON STRUCTURE METHOD OF VERY HIGH-SPEED MULTIDIMENSIONAL DIGITAL FILTER USING MULTIRATE SIGNAL PROCESSING

基于多信号处理的超高速多维数字滤波器的结构方法研究

基本信息

批准号：
12650358
负责人：
TSUNEKAWA Yoshitaka
金额：
$ 1.92万
依托单位：
IWATE UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
2000
资助国家：
日本
起止时间：
2000 至 2002
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-12650358/
关键词：
DIGITAL FILTERS DISTRIBUTED ARITHMETIC ADAPTIVE FILTER BLOCK ALGORITHM HIGH SPEED LOW POWER DISSIPATION VLSI ARCHITECTURE 2次元FIR VISIアーキテクチャ 2次元ディジタルフィルタマルチレート高精細画像プロセッサ VLSI

项目摘要

1. This research proposed a high-performance VLSI architecture for separable denominator 2-D state space digital filters based on reduced-dimensional decomposition. To obtainhigh-speed implementation, we aplied the highly parallel architecture based on the block algorithm. For the purpose of higher speed, small overhead is kept by using the distributed arithmetic of which processing time depends only on word length. Further, we can substantially decrease power dissipation by taking advantage of not the conventional distributed arithmetic using ROM's, but the method using the optimum function circuits which we have previously proposed. As a result of VLSI evaluation, we showed that this proposed architecture was very efficient for super high definition image.2. Firstly, we proposed and analyzed the LMS adaptive filter using distributed arithmetic (DA-ADF), which used no multipliers (that is multiplier-less). Our proposed DA-ADF is a high-performance adaptive filter which has performances of high speed and small output latency, good convergence speed, small-scale hardware and lower power dissipation for higher order, simultaneously.Secondly, for the purpose of further higher speed, we proposed block LMS algorithm using distributed arithmetic (BDA) and multi-memory block structured BDA (MBDA). To enable the pipelined processing, we applied an new update method to these algorithms. We called the method "priority update". Moreover, we proposed an efficient VLSI architecture of MBDA-ADF, and evaluated the sampling rate and output latency. As a result, our MBDA-ADF can achieve very high sampling rate and smal output latency.

1.提出了一种基于降维分解的可分离分母二维状态空间数字滤波器的高性能VLSI结构。为了获得高速实现，我们采用了基于分块算法的高度并行结构。为了提高处理速度，采用了处理时间仅与字长有关的分布式算法，保持了较小的开销。此外，我们可以大大降低功耗，利用不是传统的分布式算法使用ROM的，但使用的方法，我们以前提出的最佳功能电路。作为VLSI评估的结果，我们表明，该架构是非常有效的超高清图像.首先，我们提出并分析了基于分布式算法的LMS自适应滤波器（DA-ADF），它不使用乘法器（即无乘法器）。本文提出的DA-ADF是一种高性能的自适应滤波器，它具有速度快、输出延迟小、收敛速度快、硬件规模小、高阶功耗低等优点。其次，为了进一步提高滤波器的速度，本文提出了基于分布式算法（BDA）和多存储器块结构BDA（MBDA）的块LMS算法。为了使流水线处理，我们应用了一种新的更新方法，这些算法。我们称之为“优先级更新”。此外，我们提出了一个有效的MBDA-ADF的VLSI架构，并评估了采样率和输出延迟。因此，我们的MBDA-ADF可以实现非常高的采样率和小的输出延迟。