FPGA design method based on self-organization maps.

布局过程是现场可编程门阵列设计流程中计算量较大的过程之一。虽然SA(模拟退火法)等非确定性算法已经成功地解决了这一问题，但它们的运行速度较慢。我们将神经网络方法引入到FPGA布局中，这是一种Kohonen SOM(SEFL Organizing Feature Maps)方法。在我们的方法中，重要的是表示网表的特征。然而，仅使用连接矩阵作为输入向量在计算资源和时间上是不够的。本文提出了一种基于Shimbel指数的输入向量。我们还讨论了三种图形距离测量方法，以提高布局质量。在评估中使用了一些基准电路，与基于SA的VPR相比，我们的方法可以减少计算时间。

A placement process is one of the heavily computational process in FPGA(Field Programmable Gate Array) design flow. Although nondeterministic algorithms such as SA(Simulated Annealing) algorithm are successful in solving this problem, they are known to be slow. We have been introduced neural network approach which is a Kohonen SOM(Sefl Organizing feature Maps) to FPGA placement. In our method, it is important to represent the features of netlists. However, it is not enough to sufficient for using only connection matrix as a input vectors in terms of computational resources and time. In this paper, we proposed input vector based on a shimbel index. We also discuss three graph distance measurement to enhance placement quality. Our method can improve computational time compared with SA based VPR using some benchmark circuits in the evaluation.