Development of aHost-Based IPS Processor with a Reconfigurable Logic for High-Speed and Low-Power Operations

在本研究中，一个IPS（入侵防御系统）处理器，这是用于移动的计算机上开发。该处理器由防火墙逻辑单元和可重构逻辑单元组成。防火墙逻辑单元的防火墙功能由硬件逻辑来实现。该单元对于低功耗操作和减少签名数量很有用。可重构逻辑单元由常规逻辑单元和用于时序调整的逻辑单元组成。采用高速低功耗设计方法，设计了两个8位加法器电路。一种是使用传统的逻辑单元，另一种是使用传统的逻辑单元和用于定时调整的逻辑单元。比较这些电路的面积的结果是，使用逻辑单元进行定时调整的电路的面积减少到28.5%。

In this study, an IPS (Intrusion Prevention System) processor which is used on mobile computers is developed. The processor is composed of Firewall Logic Unit and reconfigurable logic cells. The firewall function of Firewall Logic Unit is executed by hardware logic. The unit is useful for low-power operations and reduction in number of signatures. The reconfigurable logic cells are composed of conventional logic cells and logic cells for the timing adjustment. Two 8-bit adder circuits are designed by design method for high-speed and low-power operations. One is the use of conventional logic cells and the other is the use of conventional logic cells and logic cells for the timing adjustment. The results of comparing areas of these circuits are the area of the circuit using logic cells for the timing adjustment is reduced to 28.5%.