Development of aHost-Based IPS Processor with a Reconfigurable Logic for High-Speed and Low-Power Operations

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In this study, an IPS (Intrusion Prevention System) processor which is used on mobile computers is developed. The processor is composed of Firewall Logic Unit and reconfigurable logic cells. The firewall function of Firewall Logic Unit is executed by hardware logic. The unit is useful for low-power operations and reduction in number of signatures. The reconfigurable logic cells are composed of conventional logic cells and logic cells for the timing adjustment. Two 8-bit adder circuits are designed by design method for high-speed and low-power operations. One is the use of conventional logic cells and the other is the use of conventional logic cells and logic cells for the timing adjustment. The results of comparing areas of these circuits are the area of the circuit using logic cells for the timing adjustment is reduced to 28.5%.