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Development of aHost-Based IPS Processor with a Reconfigurable Logic for High-Speed and Low-Power Operations

Development of aHost-Based IPS Processor with a Reconfigurable Logic for High-Speed and Low-Power Operations
开发具有可重构逻辑的基于主机的 IPS 处理器,以实现高速和低功耗操作
批准号:
21700064
负责人:
SATO Tomoaki
金额:
$2.75万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Young Scientists (B)
财政年份:
2009
资助国家:
日本
项目状态:
已结题
起止时间:
2009 至 2010

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中文摘要
翻译
在本研究中,一个IPS(入侵防御系统)处理器,这是用于移动的计算机上开发。该处理器由防火墙逻辑单元和可重构逻辑单元组成。防火墙逻辑单元的防火墙功能由硬件逻辑来实现。该单元对于低功耗操作和减少签名数量很有用。可重构逻辑单元由常规逻辑单元和用于时序调整的逻辑单元组成。采用高速低功耗设计方法,设计了两个8位加法器电路。一种是使用传统的逻辑单元,另一种是使用传统的逻辑单元和用于定时调整的逻辑单元。比较这些电路的面积的结果是,使用逻辑单元进行定时调整的电路的面积减少到28.5%。
英文摘要
In this study, an IPS (Intrusion Prevention System) processor which is used on mobile computers is developed. The processor is composed of Firewall Logic Unit and reconfigurable logic cells. The firewall function of Firewall Logic Unit is executed by hardware logic. The unit is useful for low-power operations and reduction in number of signatures. The reconfigurable logic cells are composed of conventional logic cells and logic cells for the timing adjustment. Two 8-bit adder circuits are designed by design method for high-speed and low-power operations. One is the use of conventional logic cells and the other is the use of conventional logic cells and logic cells for the timing adjustment. The results of comparing areas of these circuits are the area of the circuit using logic cells for the timing adjustment is reduced to 28.5%.
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Development of a shift register for Firewall Circuits by Wave-Pipelined Operations
通过波流水线操作开发防火墙电路移位寄存器
DOI: --
发表时间: 2010
期刊: Proc. of 2010 International Workshop on Information Communication Technology
影响因子: --
作者: [Tomoaki Sato, Kei Ito, Keisuke Saito, Phichet Moungnoul, Masa-aki Fukase]
通讯作者: Masa-aki Fukase
Performance of IR-UWB PSM and BPM over S-V Channel Model
IR-UWB PSM 和 BPM 在 S-V 通道模型上的性能
DOI: --
发表时间: 2010
期刊: Proc. of 2010 International Workshop on Information Communication Technology (ICT2010)
影响因子: --
作者: [Phichet Moungnoul, Anan Sopin, Tomoaki Sato]
通讯作者: Tomoaki Sato
Double Cipher Implementation in Ubiquitous Processor Chip
无处不在的处理器芯片中的双重密码实现
DOI: --
发表时间: 2011
期刊: Proc. of ECTI-CON2011
影响因子: --
作者: [Masa-aki Fukase, Harunobu Uchiumi, Takumi Ishihara, Naomichi Mimura, Kazuki Narita, Tatsuya Takaki, Tomoaki Sato]
通讯作者: Tomoaki Sato
Sustainable ICT Education Using a Student's Own PC
使用学生自己的 PC 进行可持续的 ICT 教育
DOI: --
发表时间: 2010
期刊:
影响因子: --
作者: [T.Sato, S.Imaruoka, M.Fukase, Tomoaki Sato, Tomoaki Sato]
通讯作者: Tomoaki Sato
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