Chip level timing analysis of 10 billion transistors schale

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With the progress of the miniaturization technology of integrated circuits, VLSI chip becomes able to mount more than 10 billion transistors. However, it faces timing reliability issues. This research aims at the technical establishment which conducts timing analysis in a chip level at high speed to the integrated circuit in consideration of manufacture variation, power supply voltage, heat change, and the aged deterioration of a transistor. It aims at visualizing the generating part and factor of a timing error on various physical conditions considered, and raises reliance and extension-of-life-span design of the complicated next-generation integrated circuit.Through the research period, (A) timing hotspot visualization system, (B) timing analysis system based on thermal and IR drop, and (C) Statistical timing model and analysis system which considers NBTI degradation and variation.