Study on a framework for auto generation and optimization of HPC accelerator architectures

本文重点研究了具有代表性的高性能计算之一的模板计算和元胞自动机计算的算法领域，并研究了一个框架来自动生成它们的加速硬件，用于fpga的可重构计算。在这个项目中，我们开发了一个基于fpga的收缩阵列的模板编译器和一个基于fpga的流计算加速器的高级综合编译器。它们是fpga高效可重构高性能计算的重要基础技术。

We have focused on an algorithm domain of the stencil computation and cellular automata computation that is one of the representative high-performance computations, and then studied a framework to automatically generate their acceleration hardware for reconfigurable computation with FPGAs. In this project, we have developed a stencil compiler for an FPGA-based systolic array and a high-level synthesis compiler for FPGA-based stream-computing accelerators. They are significant and fundamental technologies for highly productive reconfigurable high-performance computation with FPGAs.