Study on a framework for auto generation and optimization of HPC accelerator architectures

本文针对模板计算和元胞自动机计算这两种高性能计算的典型算法领域，研究了一种基于FPGA的可重构计算加速硬件自动生成框架。在本项目中，我们为基于FPGA的脉动阵列开发了模板编译器，并为基于现场可编程门阵列的流计算加速器开发了高级综合编译器。它们是利用现场可编程门阵列实现高效率、可重构的高性能计算的重要基础技术。

We have focused on an algorithm domain of the stencil computation and cellular automata computation that is one of the representative high-performance computations, and then studied a framework to automatically generate their acceleration hardware for reconfigurable computation with FPGAs. In this project, we have developed a stencil compiler for an FPGA-based systolic array and a high-level synthesis compiler for FPGA-based stream-computing accelerators. They are significant and fundamental technologies for highly productive reconfigurable high-performance computation with FPGAs.