Energy-Aware HW/SW Co-Design Method for Fine-Grained Power-Gated VLIW Processors

功率门控技术是目前公认的大幅度降低泄漏能量的技术，但其性能存在一定的缺陷。本研究提出细粒度功率门控VLIW处理器的泄漏能量感知软硬件协同设计方法。VLIW处理器有多个指令槽，功率门控应该应用于每个功能单元。本研究提出两种方法：能量感知指令调度方法和架构探索方法。能量感知指令调度方法考虑了功率门控效应，对指令调度进行了优化。体系结构探索方法试图找到帕累托最优的候选体系结构，特别关注功能单元的数量和指令分配。实验结果表明了该方法的有效性。

Power gating is well-known technique to reduce the leakage energy drastically, but it suffers from performance penalty. This research proposes leakage energy aware HW/SW co-design method for fine-grained power gated VLIW processors. VLIW processors have multiple instruction slots, and power gating is supposed to be applied to each functional units. This research proposes two methods: energy-aware instruction scheduling method and architecture exploration method. Energy-aware instruction scheduling method optimizes the instruction scheduling taking into account power gating effects. Architecture exploration method tries to find Pareto optimal architecture candidates, and especially focuses on the number of functional unit and instruction assignment. Experimental results show the efficiency of proposed methods.