A High-Performance High-Reliable Architecture for Better Energy Efficiency and Wear-out Toleration

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To tolerate the increasing electronic error, the traditional way in microprocessor is to use dual or triple modular redundancy for high-dependable execution, which does not show good energy efficiency. In this research, targeting at a low-power high-performance fault toleration, the following points have been carried out: 1. A fusion of temporal and spatial redundancy: 2. A non-TMR based scheme to locate the permanent failure; (3) Architectural method to aid NBTI effects. The results of this research have been published in 7 journal papers and 9 international conference papers with referee.