High deposition rate superfill copper

3-D集成电路，利用垂直金属内部芯片连接，最终将提供更高的系统性能，更小的外形尺寸和更低的成本，与目前主要的2-D设备格式相比。它们使同质或异质器件能够在一个小封装中堆叠，从而开辟了许多新的应用。目前，垂直铜连接（tsv）的制造成本限制了该技术的应用。形成先进TSV的成本中约有50%与Cu的电化学沉积（ECD）和现场Cu去除步骤有关。我们的目标是通过改善高纵横比通孔内的输运动力学，大幅提高ECD Cu的沉积速率（>2x）。这一进展所实现的成本降低将有助于使TSV获得更多的应用。

3-D Integrated circuits, utilizing vertical metal inter die connections, will ultimately provide improved system performance, smaller form factor and reduced cost when compared to current largely 2-D device formats. They enable the stacking of homogeneous or hetrogenous devices in a small package which in turn will opens up many new applications. Currently the cost associated with the fabrication of the vertical Cu connections called Through Silicon Vias (TSVs) is limiting the adoption of this technology. Appoximately 50% of the cost of the formation of an advanced TSV is associated with the Electrochemical Deposition (ECD) of Cu and the field Cu removal step. We aim to substantially increase (>2x) the deposition rate of the ECD Cu by improving the transport kinetics within the high aspect ratio vias. Cost reductions achieved by this advance will help make TSV accessable for more applications.