Scalable implementation of hybrid spin qubits in CMOS-compatible devices

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A quantum computer will solve problems that are impossible even for classical supercomputers to solve in reasonable time. Theoretical studies have indicated an expected "quantum speed-up" over classical computers in applications such as cryptography, optimization and simulation. However, to achieved this quantum speed-up requires large number of accessible qubits with extremely high fidelity. Current quantum technology offered few tens of qubits with barely satisfactory multi-qubit gate fidelity, and still it faces scaling up issues both in qubits as well as in peripheral control circuitry. Researchers have demonstrated qubits constructed from the spin states of impurity donors or quantum dots in silicon(Si) substrates with record-high coherence times. Meanwhile, Si-based qubits could potentially scale up benefiting from the standard industrial complementary metal oxide semiconductor (CMOS) processes. CMOS processes have been developing for the past few decades and state-of-art process can produce billions of transistors within a cm-scale chip. Therefore, silicon spin qubits are very promising candidates for quantum computing based on its robust storage of quantum information and possibility to leverage mature manufacturing processes. This project will investigate a possible spin qubit implementation based on silicon Nanowire Field Effect Transistors (Si NW-FETs). Quantum dots, or potentially donors located within the FET channel, will be used as the qubits, and strategies for using global control to improve scaling will be investigated. Qubit coupling using floating gates will be evaluated, and techniques to achieve high-fidelity spin read-out using reflectometry will be optimised.