Reconfigurable computing techniques and VLSI implementations for IT security and image processing

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Reconfigurable computing is intended to fill in the gap between hardware and software, potentially achieving a much higher performance than software, while maintaining a higher level of flexibility than hardware. By placing the computational-intense portions of an application onto the reconfigurable hardware, it will accelerate the system performance greatly. The implementations of cryptography services for IT (Information Technology) security on wireless devices and embedded systems present a great challenge, particularly to the memory, power, computation resources, and mobility constraints. Reconfigurable computing can serve as an excellent platform for hybrid cryptosystems on restricted computing environments and wireless devices. The reconfigurable architectures increase the flexibility of system schemes and the efficiency of computation resources, and reduce the total cost. Moreover, hardware piracy issues cause huge profit loss in the IT industry. In this research project, we also examine how to use the reconfigurable computing/architecture to protect the hardware IP (Intellectual Property). Image processing plays a crucial role in areas of medicine, crime prevention and investigation, publishing, entertainment, education, and scientific research. It has become urgent to find the desired images from an image database quickly and automatically. This technique is known as content-based image retrieval (CBIR). However, little research has been done to use the reconfigurable computing technique to speed-up the image retrieval. We will explore new approaches of image retrieval and propose efficient algorithms and fast implementation to improve the retrieval rate of current CBIR systems. My research goal is to investigate and design reconfigurable architectures with low costs, high speeds, and high flexible structures to support real-time online secure data communications, hardware IP (Intellectual Property) protection, and image retrieval. The proposed reconfigurable architectures have regular structures and are very suitable for high speed VLSI implementation.