New algorithms and techniques to implement scalability in VLSI physical design

在 VLSI 物理设计中实现可扩展性的新算法和技术

• 批准号: 262463-2009
• 负责人: Behjat, Laleh
• 金额: $ 1.82万
• 依托单位: University of Calgary
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2014
• 资助国家: 加拿大
• 起止时间: 2014-01-01 至 2015-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=548030
• 关键词: New; algorithms; techniques; implement; scalability

Advances in the Integrated Circuits (IC) technology have resulted in tremendous growth, making ICs prevalent in our lives. Today's ICs contain over a billion switching elements, transistors, which are connected through a complicated network of wires. The total length of these wires is estimated to be around three kilometers for every square centimeter of manufactured IC. All these transistors need to be placed (placement stage) and their interconnecting wires need to be routed (routing stage). The placement and routing stages need to be performed optimally and efficiently.

集成电路(IC)技术的进步带来了巨大的增长，使IC在我们的生活中变得普遍。今天的集成电路包含超过10亿个开关元件和晶体管，这些元件通过复杂的导线网络连接在一起。据估计，每制造一平方厘米的集成电路，这些电线的总长度约为3公里。所有这些晶体管都需要放置(贴装阶段)，它们的互连线需要布线(布线阶段)。布局和布线阶段需要以最佳和高效的方式进行。