Synthesis of Heterogeneous Multi Processor System-on-Chip with Optical Interconnect

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The market for embedded systems is growing rapidly while applications are being designed to expose the inherent parallelism of the underlying algorithms. Conventional processors and on-chip communication architectures do not scale well with the stringent performance and power requirements of embedded applications. Current trends in chip design indicate increasing number of transistors on chip and on-chip availability of diverse technologies. These trends have enabled the fabrication of multi-processor chips interconnected with integrated optical communication architectures. This technology promises to create systems that provide high performance and low power consumption. However, the manual design of such systems is a time consuming and error prone process, thereby negatively impacting the cost and quality of such systems. The long term objective, addressed by this research program, is to automatically synthesize the optimal set of processing elements interconnected with the most efficient communication architecture from a parallel application model. We propose the use of application specific processors (ASPs) for the computational part of the system, and integrated optics for the interconnect architecture. Over the next five years, we propose to develop: (1) automatic synthesis of ASP cores from parallel application models, (2) novel methodologies and tools to facilitate efficient design and evaluation of scalable Optical Network-on-Chip for given power, performance and reliability constrains, and (3) automatic mapping of parallel applications to systems with optical network of heterogeneous ASP cores. We will use applications from consumer electronics, bio-medical, and avionics application domains to drive our research efforts. These application domains are key drivers of the Canadian economy and solutions for efficient implementation of such applications will provide the competitive edge to Canadian design companies.