Fault Model-Based Testing

基于故障模型的测试

• 批准号: RGPIN-2017-03900
• 负责人: Petrenko, Alexandre
• 金额: $ 1.68万
• 依托单位: Centre de recherche informatique de Montréal
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2019
• 资助国家: 加拿大
• 起止时间: 2019-01-01 至 2020-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=679252
• 关键词: Fault; Model; Based; Testing

The proposed research focuses on a model-based testing from Finite State Machine (FSM) and Input/Output Transition System (IOTS) models, including their extensions. It advocates fault model-based testing, which draws constantly growing interests of both, researchers and test practitioners. One of the reasons for this is the fact that the program/specification coverage does not provide any guarantee for fault detection. The dictum of Dijkstra could be mentioned here: testing can be used to show the presence of bugs, but never to show their absence. The proposed research is aimed at finding an answer to the question: can testing at least guarantee that no faults of certain types are left? The challenge then is how faults should be modeled. We define a fault model as a tuple of a specification, fault domain, and conformance relation. A fault domain as a set of all possible submachines of a given nondeterministic machine, called a mutation machine of a given specification machine. The mutation machine contains the specification and extends it with a number of mutated transitions modelling potential faults. In our recent work, we developed an approach for test generation which is based on logical encoding and SMT-solving. Considering this approach as a starting point, we plan to investigate a general fault model-based testing framework to deal with a variety of state-oriented models, from classical FSM and IOTS models to their symbolic extensions reaching the level of extensions found in state-oriented models used in model-driven development of critical applications, such as Simulink Stateflow and UML state machines as well as activity and sequence diagrams. The goal of this project is to develop scalable testing approaches (supported by prototype tools) for developing tests with a coverage guarantee for fault models chosen by the domain experts based on the history of a product development, company's specifics and their test assumptions.

本文的研究重点是基于有限状态机（FSM）和输入/输出转换系统（IOTS）模型的测试，包括它们的扩展。它提倡基于故障模型的测试，引起了研究人员和测试实践者不断增长的兴趣。其中一个原因是程序/规范覆盖率不提供故障检测的任何保证。Dijkstra的格言可以在这里提到：测试可以用来显示bug的存在，但永远不能显示它们的不存在。拟议的研究旨在找到问题的答案：测试是否至少能保证不留下某些类型的错误？接下来的挑战是如何对故障进行建模。我们将故障模型定义为规范、故障域和一致性关系的元组。故障域是一个给定的不确定机器的所有可能的子机器的集合，称为给定规范机器的突变机。突变机包含规范，并通过对潜在故障进行建模的许多突变转换对其进行扩展。在我们最近的工作中，我们开发了一种基于逻辑编码和SMT求解的测试生成方法。考虑到这种方法作为一个起点，我们计划研究一个通用的故障模型为基础的测试框架，以处理各种面向状态的模型，从经典的FSM和IOTS模型，其符号扩展达到的扩展水平，发现在面向状态的模型中使用的模型驱动的关键应用程序的开发，如Simulink Stateflow和UML状态机以及活动和序列图。该项目的目标是开发可扩展的测试方法（由原型工具支持），用于开发测试，并保证由领域专家根据产品开发历史，公司的具体情况及其测试假设选择的故障模型的覆盖率。