Advanced-modulation circuits for low-power scalable wireline transceivers

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The emergence and popularity of technologies such as machine learning, autonomous driving and cloud storage & computation has created an urgent demand for the rapid evolvement of high-speed input-output (I/O) circuits. Such platforms demand exceedingly large data bandwidth with low power consumption, posing significant design challenges for the current architectures and an uncertain path to scalability. This collaborative project between UBC and Intel will focus on addressing these challenges. This proposed research aims to develop wireline integrated circuits for low-power transceivers that support advanced modulation formats not currently being used by wireline data links. The work to be accomplished in this project primarily involves a mix of modelling, design and measurement. The target application is next-generation wireline solutions and products for the ICT industry.