Development of Energy-Efficient High-Resolution Analog-to-Digital Data Converters for Power-Constrained Applications

点击翻译按钮获取中文摘要

Energy-efficient high-resolution analog-to-digital converters (ADCs) are essential for a broad range of emerging applications including autonomous sensors for environmental monitoring and internet-of-things, portable medical devices for 24/7 patient health monitoring, miniaturized implantable medical devices for detecting micro-scale biomedical signals, embedded sensors for structure monitoring, machine monitoring, and advanced manufacturing, to name a few. Analog-to-digital converters operated with a low supply voltage with the power efficiency of a few femto joules per conversion step and a resolution exceeding 12 bits are required in these applications. Successive approximation register (SAR) analog-to-digital converters emerged in 1950s and debuted in complementary metal-oxide-semiconductor (CMOS) in 1970s distinguish themselves from pipelined and delta-sigma ADCs with low power consumption, excellent technology compatibility, a wide range of conversion rate, and a good resolution, and are ideal candidates for these applications. This research project will build upon the prior research and expertise of the applicant in mixed-mode signal processing and develop low-power high-resolution SAR ADCs for power-constrained applications. Research will be focused on the development of new low-power techniques to minimize the power consumption of SAR ADCs, new circuit topologies and techniques to minimize the impact of the noise, offset, and meta-stability of comparators, new energy-efficient algorithms and their energy-efficient realization to minimize the impact of capacitor mismatch in capacitive digital-to-time converters, and hybrid SAR ADCs that make use of time-based signal processing in design of SAR ADCs so as to utilize the merits of technology scaling to achieve minimum power and silicon consumption without sacrificing performance.