嵌入式领域中，图像、信号处理等应用的复杂度已显著增加，单处理器已无法满足应用对计算能力和功耗效率的要求。作为一类特殊的异构众核结构，众核ASIP可显著提升处理器的计算能力、可扩展性和功耗效率。但众核ASIP在设计方法学方面面临3个亟待决绝的基础性问题：如何高效地分析和并行化应用算法，如何高效地将算法中的任务和通信映射到系统中的处理器核和通信通道上，如何高效地针对关键算法定制专用指令以进一步提升效率。. 针对上述挑战，本项目提出一种基于标准C/C++程序的算法并行化和算法高层次模型提取技术，提出一种采用高层次分析、高层次模拟、周期精确模拟相结合的层次化算法映射技术，提出一种考虑众核处理器的计算/通信时间的ASIP专用指令定制技术，并基于这些技术和现有研究成果构建一个众核ASIP集成开发框架。我们希望本项目的研究成果能够辅助国产高性能专用处理器的研发，并应用于实际应用中。

The complexity of applications like image processing, digital signal processing in embedded domains, has nowadays grown to the extent that single processors cannot meet the requirement on performance and computation efficiency anymore. Many-core ASIPs (Application-Specific Instruction-set Processors), as a special type of heterogeneous many-core processors, can substantially improve processors’ performance, scalability, and computation efficiency. However, many-core ASIPs are faced with 3 fundamental challenges arising from design methodologies: how to efficiently analyze and parallelize application algorithms, how to rapidly and efficiently map computation and communication tasks from applications on the processor cores and communication channels of many-core architectures, and finally, how to customize the datapaths of processor cores according to applications’ characteristics to further improve computation efficiency.. To provide efficient solutions to these design challenges, this project proposes a novel application parallelization technology which can automatically extract the KPN models of applications based on standard C/C++ programs; proposes a hierarchical algorithm mapping method that adopts high-level analysis, high-level simulation, and cycle-accurate simulation to reduce design time as well as improve evaluation accuracy; proposes an novel custom instructions generation technology that automatically generates efficient custom instructions according to the computation/communication characteristics of many-core systems. Finally, we will combine these technologies with our achievement already achieved to construct a systematic and automatic framework for the design of many-core ASIPs. We hope the achievement of this project could assist the design of national high-performance many-core Processors..