静态随机存取存储器（SRAM）在数字芯片与数字系统中有着广泛的应用，也是制约数字系统性能与应用场景的关键模块。本项目面向物联网芯片、深度学习芯片等新一代数字芯片对SRAM功耗日益严苛的要求，开展“基于动态自适应堆叠与电荷域读写技术的SRAM阵列芯片研究”。针对电压堆叠的SRAM阵列，本项目提出的自适应堆叠技术可以实现堆叠结构的动态调整，让阵列保持最低静态电流漏电的状态，并有可能突破电压堆叠层数不超过2的实际限制；针对电压堆叠后的SRAM单元读写困难的问题，本项目提出了动态电荷域读写技术，保证堆叠后的SRAM可以稳定、高速地实现读写。以上创新性电路技术具有强大的工艺迁移性，可为各CMOS工艺节点下的SRAM阵列均带来更低的功耗。基于以上创新技术，本项目拟研制CMOS样片，实现静态功耗在10fW/bit量级，为同工艺标准SRAM五十分之一以下的超低功耗SRAM芯片。

SRAM arrays are widely used in digital integrated circuit systems. Its performance has always been a key limiting factor to the speed, power, and area of the fully integrated digital system. In this proposal, we address the rising demand to minimize the power consumption of integrated SRAM arrays in recent years for Internet-of-Things (IoT) and deep learning related applications, and focus our research efforts on the topic “Low Power SRAM Array Using Adaptive Voltage Stacking and Charge Domain Read-and-Write Peripheral Circuits”. Here, we propose adaptive voltage stacking as a technique that enables aggressive voltage stacking in SRAM arrays by dynamically adjusting the structure of the actual voltage stack, leading to the potential to achieve a stable voltage stack higher than 2, an observed highest practical record ever reported. We also propose a dynamic charge domain read-and-write circuit as a part of solution to the peripheral circuits for densely stacked SRAM arrays, ensuring stable read and write operations at a high energy efficiency. The above techniques give SRAM arrays lower power consumption regardless of the chosen technology node. We aim to implement an SRAM array using techniques mentioned above, targeting a static power reduction of 50 times compared to SRAMs made in the same technology node, and approaching 10 fW/bit in terms of the absolute leakage power.