基于栅极调控的隧穿二极管结构的二维半导体薄膜水平异质结隧道场效应晶体管

隧道场效应晶体管（TFETs）被认为是最有前途的后CMOS器件。TFETs器件具有极低的工作电压以及不牺牲ON/OFF比的快速能量转换效率。然而由于传统半导体材料TFETs面临着众多问题，比如：弱的栅极调控能力；高禁带宽度导致的长隧穿距离和低工作电流；界面陷阱导致的漏电。因此使用传统材料难以制备出高性能的TFETs器件。然而利用二维材料可以巧妙的克服上述问题。比如利用二维材料异质结可显著降低载流子隧穿距离。另外二维材料表面没有悬空键可抑制了陷阱态的产生。结合二维材料优异的特性，我们的目标是研制基于栅极调控隧穿二极管结构的二维半导体水平异质结隧穿场效应晶体管。本项目提出的两步外延生长方法，不光可以突破水平结构隧穿场效应晶体管所要求的极其严格的栅极对准，而且可以实现材料的简并掺杂以及两种二维材料的无缝对接。辅以严格的理论计算与器件仿真，完全可以首次制备出高性能TFETs器件。

Tunnel field-effect Transistors (TFETs) are considered the most promising post-CMOS switches, since they provide abrupt switching characteristics, i.e., small (<60 mV/decade) sub-threshold swing (SS), and hence enable ultra-small supply voltage Vdd and switching energy without compromising ON-OFF current ratio, which is un-achievable in conventional CMOS devices. However, it has been found extremely challenging to recover the expected TFET performance on bulk material platform, which results from 1) inefficient gate control leading to large tunnel barrier width and low ON-current; 2) large band gap leading to high tunnel barrier and low ON-current; 3) interface trap induced leakage current leading to large SS. Utilizing the emerging 2D materials for TFET application can potentially overcome these issues, because 2D materials have 1) sizable band gap and band alignment that allow staggered- or even broken-gap type heterojunction design and lowering of tunnel barrier height, 2) ultra-thin body that provides excellent gate control and hence lowers tunnel barrier width, and 3) pristine surface that greatly suppresses the trap generation. Therefore, it is very timely and necessary to explore 2D materials based TFETs at the present stage. The key objectives of the proposed work will be to demonstrate 2D material based high-performance tunnel FETs. Basic approaches that will be used include developing a two steps 2D heterojunction synthesis method, which not only allows the precise formation of the gate on the edge of junction but also provide a seamless junction with minimum defects. With the help of simulation and modeling, device structure can be designed and optimized to achieve high performance TFET devices for the first time.