800G光通信CMOS单片集成PAM8光电接收芯片关键技术研究

全球海量信息传输和高性能计算的强烈需求极大的推动了光电互连系统的发展和应用，但目前通用的混合式光电芯片系统存在成本高和功耗大的问题。本课题将对CMOS单片集成PAM8光电接收芯片中的三项关键技术开展理论研究和电路验证，拟通过把CMOS单片集成和PAM8调制模式相结合，明确调制模式、线性度和数据率之间的理论关系，分析超低纹波均衡和线性度之间的相互影响，揭示多通道间串扰和系统误码率的内在关联，建立硅基雪崩空间调制光电探测器和高速线性电路单片集成的设计方法。本课题拟采用标准CMOS工艺实现一款低成本和低功耗的PAM8高速线性CMOS全集成光电接收芯片:系统单通道数据率达到224Gb/s，系统误码率<1E-3，光灵敏度达到-5dBm，总功耗100mW，总谐波失真<3%。本课题将对推动我国在800GbE高端光通信芯片系统领域的创新提供重要的基础研究支持。

The dramatically increasing demand for massive data transmission all over the word has greatly stimulated the development and application of optoelectronic integrated circuits (OEIC) system. However, the conventional hybrid OEIC system has the problem of high cost and large power consumption. This project will focus on research on key techniques of 800GbE monolithic PAM8 OEIC in standard CMOS. By combining monolithic integration and high-level pulse-amplitude modulation (PAM), we will investigate the theoretical relationship between system linearity and data rate, explore the inner connection between multi-channel crosstalk and system bit-error-rate (BER), obtain the model of complimentary equalizer circuit with ultra-low ripple, and build the methodology of integrating photodetectors and high-speed linear circuits onto one CMOS substrate. This research will realize one low-cost and low-power PAM8 high-speed linear monolithic OEIC in standard CMOS technology, achieving: 224Gb/s data rate per lane, BER<1E-3, -5dBm optical sensitivity, 100mW power consumption, total harmonic distortion<3%. This research will give an important support to boost the fundamental research of our countries’ high-speed optical communication circuits, especially 800 Gigabit Ethernet (GbE) applications.