基于超陡亚阈值摆幅器件的低功耗SRAM存储系统关键技术研究

受玻尔兹曼热力学限制，传统硅基晶体管的亚阈值摆幅存在理论极限，严重阻碍了SoC芯片功耗的进一步降低。基于带带隧穿导通机制的隧穿场效应晶体管因具有超陡亚阈值摆幅、较低关态电流且与CMOS工艺兼容等特点在低功耗设计领域表现出很强的竞争优势。因此，本项目拟基于超陡亚阈值摆幅的隧穿晶体管对SoC核心存储部件SRAM进行低功耗设计。主要研究内容为：①基于读写分离及写路径动态切断机制，并结合工艺因素实现对隧穿晶体管型存储单元的拓扑设计和可靠性评估；②基于次级时钟驱动的并行架构及多参数联合优化能耗模型，实现集成隧穿晶体管的SRAM存储系统架构优化及能耗建模；③针对器件差异性，设计兼容隧穿晶体管的SRAM存储系统关键电路，并利用蒙特卡洛方法完成电路的可靠性分析。本项目最终将在CMOS工艺下实现集成隧穿晶体管的低功耗SRAM芯片原型，促进国产超低功耗SoC芯片的研制，进而为下一代物联网的发展提供技术支持。

Limited by Boltzmann thermodynamics, the theoretical limit of the subthreshold amplitude of traditional silicon-based transistor seriously hinder the further reduction of the power consumption of System-on-Chip (SoC). The tunneling field effect transistor (TFET) device based on band to band tunneling mechanism has shown strong competitive advantages in the field of low-power design due to its characteristics such as ultra-steep sub-threshold swing, low off-state current and high compatibility with CMOS process. Hence, based on the TFET device with ultra-steep sub-threshold swing, this project intends to design the low power SRAM system, which acts as the core memory component of SoC. The main research contents of this project include: ① Combined with process factors, the topological study and the reliability evaluation of the tunneling transistor memory cell will be executed on the base of the mechanism of read/write separation and write path dynamic cut-off; ②Based on the secondary clock-driven parallel architecture and optimized energy consumption model with joint multi-parameter, architecture optimization and energy consumption modeling will be carried out for SRAM storage system with integrated TFET devices; ③ The design of the key circuits for SRAM storage system with the compatible tunneling transistor will be realized according to the device difference, and the reliability analysis of the circuit is completed by Monte Carlo method. Finally, the implementation of this project will form the prototype of a low-power SRAM memory chip integrated with TFET devices under CMOS technology and further promote the development of domestic ultra-low power SoC, which provides technical support for the development of the next generation of Internet of things in China.