面向单载波超400Gb/s相干光通信的堆叠型CMOS超高速线性光收发前端芯片研究

随着基于强度调制-直接检测(IMDD)的光互连技术在速率上接近极限，以及相干光通信技术不断从长距离骨干网拓展到更短距离，相干技术下沉将成为光通信行业未来最重要的发展趋势之一。目前基于SiGe工艺的相干光通信模拟前端无法与CMOS后端实现全集成，将成为未来全面相干下沉的核心技术瓶颈。然而，基于CMOS工艺的高速模拟前端面临着噪声、线性度、带宽和输出摆幅等方面的巨大挑战，传统设计方法已不适用。本项目针对CMOS电路和相干光应用的特点，拟研究新型多电压域堆叠式线性收发前端架构，结合提出的高效率全集成多电压域电源管理策略，在架构级为CMOS电路性能提升提供支撑。在电路级，对CMOS电路面临的每一个核心问题研究新型电路结构及多维设计优化策略。通过架构和电路两个层面相结合，使CMOS相干光通信模拟前端满足应用的苛刻要求。预期在项目结束时，在基于CMOS工艺的光通信线性模拟前端研究达到国际一流水平。

As IMDD (Intensity Modulation Direct Detection) based optical links reach the speed limits, as well as the coherent communication expands from long-haul backbone network to shorter reach, the pervasion of coherent communication technology is becoming one of the most important trend in future optical communication. However, the SiGe based coherent communication analog front-ends are not able to integrate with CMOS backend, which will become the key bottleneck for coherent communication to expand its application space. Meanwhile, CMOS based analog front-ends suffer from several challenges in noise, linearity, bandwidth and output swing, etc., which can’t be solved using traditional design approaches. Therefore, in this research, based on the properties of CMOS transistor and coherent communication, we propose the novel multi-voltage domain stacked linear transceiver front-end topologies. Accompanied with our highly-efficient integrated multi-voltage domain power management scheme, we lay the architecture infrastructure for CMOS performance boost. At the circuit level, we will address every key issue with novel circuit structure and multi-dimensional design and optimization techniques. The fusion of architecture and circuit level approaches will enable CMOS to satisfy the harsh requirement to implement analog front-ends for coherent communication. At the end of this project, we expect to become top tier in the research of CMOS optical linear analog front-ends internationally.