面向48V电源系统的高集成、低损耗混合结构负载点转换器关键技术研究
批准号:
62104269
项目类别:
青年科学基金项目(C类)
资助金额:
30.0 万元
负责人:
江洋
依托单位:
学科分类:
集成电路设计
结题年份:
2024
批准年份:
2021
项目状态:
已结题
项目参与者:
江洋
中文摘要
负载点转换器是48V电源应用中为芯片系统供电的重要模块,具有高输入、高降压比、大电流等性能特点,直接关系到负载芯片的功能与性能边界。现有高变压比负载点转换技术存在拓扑结构层面的理论局限,导致传导及寄生损耗大、功率密度低等问题,严重限制了电压转换范围、输出电流水平及整体效能成本。本项目基于新型开关模式转换器框架,从结构原理、控制方法、电路设计三个层面开展研究,着力解决损耗降低及折衷优化两方面的关键科学问题。研究工作针对转换器的开关耐压、电感电流及占空比范围等设计要点,提出新型多级、多路径混合拓扑结构,实现损耗与转换范围方面的性能同步提升;利用功率级可重构技术实现变压比范围拓展;结合软开关技术及控制电路设计降低开关损耗。研究成果可促进48V电源标准下的智能汽车电子系统、数据中心及工业机器人等领域的技术进步与硬件升级,为科学研究及工程实践提供理论方法及技术参考,具有重要的科学意义和应用价值。
英文摘要
Point-of-Load (PoL) converter is an essential module for 48-V power supplied applications. It is required to be capable of processing a high input voltage, realizing a high step-down conversion ratio, as well as supporting a large output current. Existing PoL converter techniques suffer from limitations in topology level, therefore hard to meet the performance requirements, manifesting in severe conduction loss, limited switching frequency, and large component sizes. These drawbacks severely restricted the voltage conversion range, output current level, and the overall cost of the converters. This project focuses on the technical direction of Switched-Capacitor (SC) Hybrid Converter design and implementation and carries out the research from the aspects of topology principle, control methodology, and circuit design. The objective is to solve two critical scientific problems of power stage loss reduction and system cost optimization. Aiming at the topology design challenges of high switch-sustained voltage, large inductor conducting current, and extremely small duty ratio value, we propose a novel multi-stage multi-path SC hybrid topology to improve the conduction loss and duty ratio restrictions. Besides, a power stage reconfiguration technique is proposed to extend the voltage conversion range. Furthermore, we modify the corresponding switching control and driver circuit techniques to improve efficiency and reduce hardware costs. The achievements of this project can promote the performance improvement of the hardware in automotive electronic systems, data centers, and industrial robotics that powered by 48V supply standard. This research can also provide a theoretical method and technical reference for scientific research and engineering practice in the related fields, which has great scientific significance and application value.
随着数据中心、新能源汽车、工业机器人等前沿应用的普及,要求48V总线标准下的负载点(PoL)供电模块具备高变比、高密度、低损耗等性能特点。而传统buck降压转换器架构难以在上述应用场景下满足性能要求。对此,本项目开展面向48V输入电压的混合架构DC-DC转换器芯片设计研究,采用开关电容辅助路径缓解电感电流负担,从而降低DCR损耗以及优化整体功率密度。同时,通过优化拓扑结构特性,实现高低压功率开关分离使用,利用品质因数更高的低压CMOS开关晶体管向输出端传导大电流,而将高压LDMOS部署在靠近输入端,起到承受耐压但无需传导大电流的效果。项目研究基于以上概念原理,实现了多种开关器件的优化利用,改善了开关损耗。项目整体研究工作共提出了13种不同类型的混合架构拓扑结构,覆盖了从1.8V到48V的宽输入电压范围,普遍实现了高于85%的峰值效率,其中最高峰值颗高达97%。功率密度方面,在论文发表之初实现了超越前沿性能指标水平。此外,本项目研究还提出了多项针对混合架构转换器的动态增强环路控制技术,以及高集成度开关驱动技术。研究成果实现了对48V标准下PoL供电方案在转换效率、功率密度、带载能力方面的全面性能提升,具有重要的科学创新意义,以及工程实用价值。
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海外基金