Approximate Adder Circuits Using Clocked CMOS Adiabatic Logic (CCAL) for IoT Applications
Approximate Adder Circuits Using Clocked CMOS Adiabatic Logic (CCAL) for IoT Applications
复制标题
使用时钟 CMOS 绝热逻辑 (CCAL) 进行物联网应用的近似加法器电路
DOI：
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
H. Thapliyal
中科院分区：
文献类型：
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作者：
Cole Terrell;H. Thapliyal
近似算术电路是指一类算术电路，其通过故意将不准确性引入电路的输出行为来实现功率和面积效率。此外，已经提出了低功率绝热计算技术作为用于减少功率耗散的方法。为了证明混合绝热和近似计算的潜在好处，我们选择了一组近似加法器，并使用时钟CMOS绝热逻辑（CCAL）重新设计它们。我们使用45 nm工艺和Cadence Spectre模拟了我们的新型绝热近似加法器。我们的模拟结果表明，近似和绝热技术的混合在50 MHz的近似CMOS实现相比，降低了40-56%的功耗。我们的结论是，绝热和近似计算的杂交将是一个很好的设计选择，应用程序具有严格的功率和面积限制，也拥有一个公差的噪音。
Approximate arithmetic circuitry refers to a class of arithmetic circuits that achieve power and area efficiency through the intentional introduction of inaccuracies into the output behavior of the circuits. Further, low-power adiabatic computing techniques have been proposed as a method for reducing power dissipation. To demonstrate the potential benefit of hybridizing adiabatic and approximate computing, we selected a group of approximate adders and redesigned them using Clocked CMOS Adiabatic Logic (CCAL). We simulated our novel class of adiabatic approximate adders using a 45nm process and Cadence Spectre. The results of our simulations show that the hybridization of approximate and adiabatic techniques reduces power dissipation by 40-56% at 50 MHz compared to approximate CMOS implementations. We conclude that the hybridization of adiabatic and approximate computing would be an excellent design choice for applications with rigid power and area constraints that also boast a tolerance for noise.