Demonstration of improved transient response of inverters with steep slope strained Si NW TFETs by reduction of TAT with pulsed I-V and NW scaling
Demonstration of improved transient response of inverters with steep slope strained Si NW TFETs by reduction of TAT with pulsed I-V and NW scaling
复制标题
演示通过脉冲 I-V 和 NW 缩放降低 TAT，改善具有陡坡应变 Si NW TFET 的逆变器的瞬态响应
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
S. Mantl
中科院分区：
文献类型：
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作者：
L. Knoll;Q. Zhao;A. Nichau;S. Richter;G. V. Luong;S. Trellenkamp;A. Schafer;L. Selmi;K. Bourdelle;S. Mantl
本文报道了高<sub>导通电流</sub>（VDD =1.0V时为64μA/μm）的应变硅（sSi）纳米线阵列薄膜晶体管。<sub></sub>在300 K时，由于陷阱辅助隧穿（达特）的抑制，脉冲I-V测量获得了小的SS，<sub>I60</sub>为1×10<sup>- 2</sup>μA/μm。将纳米线缩放至10 nm直径极大地抑制达特的影响并改善了SS和I<sub>ON</sub>。互补TFET反相器的瞬态分析首次通过实验证明，器件缩放和改进的静电产生更快的时间响应。
We present gate all around strained Si (sSi) nanowire array TFETs with high I<sub>ON</sub> (64μA/μm at V<sub>DD</sub>=1.0V). Pulsed I-V measurements provide small SS and record I<sub>60</sub> of 1×10<sup>-2</sup>μA/μm at 300K due to the suppression of trap assisted tunneling (TAT). Scaling the nanowires to 10 nm diameter greatly suppresses the impact of TAT and improves SS and I<sub>ON</sub>. Transient analysis of complementary TFET inverters demonstrates experimentally for the first time that device scaling and improved electrostatics yields to faster time response.