Fast path selection for testing of small delay defects considering path correlations

Fast path selection for testing of small delay defects considering path correlations
复制标题

DOI:
10.1109/vts.2010.5469628
复制
发表时间:
2010-04
期刊:
2010 28th VLSI Test Symposium (VTS)
影响因子:
--
通讯作者:
Zijian He;Tao Lv;Huawei Li;Xiaowei Li
Zijian He;Tao Lv;Huawei Li;Xiaowei Li
中科院分区:
其他
文献类型:
--
作者:
Zijian He;Tao Lv;Huawei Li;Xiaowei Li

文献摘要

被引文献

相似文献

在深亚微米工艺中,延迟变化对电路性能的影响越来越大,统计时序模型已被提出来描述延迟变化。在统计时序模型下,路径测试可以检测由不同的小延迟缺陷引起的潜在延迟故障。由于路径的相关性,两条不同路径捕获的潜在延迟故障或多或少存在重叠,很难找到一个给定数目的路径来捕获最多的潜在延迟故障。本文将路径选择问题转化为最小空间相交问题,提出了一种贪婪路径选择算法,其关键是计算指定路径集合中所有路径满足时延约束的概率。在计算中采用了统计时序分析技术和逻辑分析法。实验结果表明,该方法是时间有效的,并实现了更高的概率捕获延迟故障相比,传统的路径选择方法。
Statistical timing models have been proposed to describe delay variations in very deep sub-micro process technologies, which have increasingly significant influence on circuit performance. Under a statistical timing model, testing of a path can detect potential delay failures caused by different small delay defects. Due to path correlations, the potential delay failures captured by two different paths overlap between each other more or less. It is difficult to find a given number of paths that can capture most potential delay failures. In this paper, the path selection problem is converted to a minimal space intersection problem, and a greedy path selection heuristics is proposed, the key point of which is to calculate the probability that the paths in a specified path set all meet the delay constraint. Statistical timing analysis technologies and heuristics are used in the calculation. Experimental results show that the proposed approach is time-efficient and achieves a higher probability of capturing delay failures in comparison with conventional path selection approaches.