100–166 GHz wide band high speed digital dynamic frequency divider design in 0.13 μm SiGe BiCMOS technology
100–166 GHz wide band high speed digital dynamic frequency divider design in 0.13 μm SiGe BiCMOS technology
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DOI：
10.1109/eumic.2015.7345071
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发表时间：
2015-12
期刊：
影响因子：
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通讯作者：
U. Ali;M. Bober;A. Thiede;S. Wagner
中科院分区：
文献类型：
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作者：
U. Ali;M. Bober;A. Thiede;S. Wagner
本文介绍了采用 SiGe 双极技术的数字动态分频器的设计。所提出的数字动态分频器基于两个以负反馈连接的锁存器。然而，与传统的静态分频器相比，锁存差分对被完全省略，以减少感测差分对的负载，从而扩展最大工作频率。制造了两个版本的动态分频器（A 和 B）来验证这一概念。 A 版的分频比为 2，B 版的分频比为 4。在版本 B 中，四分频比是通过在版本 A 前面级联两个传统静态分频器来实现的。电路采用 IHP 0.13 μm SiGe BiCMOS 技术制造，ft 和 fmax 分别为 300 GHz 和 500 GHz。测得输入参考自振荡频率 (SOF) 为 149 GHz。两个分频器均采用单端正弦波时钟输入，工作频率为 100 至 166 GHz。在 Vcc = 3 V 和 Vee = -1.9 V 的双电源下，版本 A 和 B 分别消耗 80 mA 和 160 mA（无输出缓冲器）。
Design of a digital dynamic divider in SiGe bipolar technology is presented in this paper. The proposed digital dynamic frequency divider is based on two latches connected with negative feedback. However, in contrast to the conventional static frequency divider the latching differential pair has been completely omitted to reduce the load for the sensing differential pair to extend the maximum operating frequency. Two versions of dynamic dividers (A and B) are fabricated to validate the concept. The divide ratio for version A is two while that for version B is four. In version B, the divide ratio of four is achieved by cascading a conventional static frequency divider by two in front of version A. The circuits are fabricated in IHP 0.13 μm SiGe BiCMOS technology with ft and fmax of 300 GHz and 500 GHz, respectively. The input referred self-oscillation frequency (SOF) of 149 GHz was measured. With single-ended sine wave clock input, both dividers are operational from 100 to 166 GHz. At dual power supply with Vcc = 3 V and Vee = -1.9 V, the version A and B consume 80 mA and 160 mA (without output buffers), respectively.