Reversible Computing with Fast, Fully Static, Fully Adiabatic CMOS
Reversible Computing with Fast, Fully Static, Fully Adiabatic CMOS
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使用快速、全静态、全绝热 CMOS 进行可逆计算
DOI：
10.1109/icrc2020.2020.00014
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
Alexander H. Hsia
中科院分区：
文献类型：
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作者：
M. Frank;R. Brocato;B. Tierney;N. Missert;Alexander H. Hsia
为了提高通用数字计算的能源效率，远远超出适用于传统数字电路的热力学限制，将需要利用可逆计算的原理。自20世纪90年代初以来，人们已经知道，基于绝热开关的可逆计算在CMOS中是可能的，尽管文献中几乎所有的“绝热”CMOS逻辑家族实际上都不是完全绝热的，这限制了它们可实现的节能。第一个实现泄漏可忽略（CRL）的真正完全绝热操作的CMOS逻辑类型不是完全静态的，这导致在存在某些非理想性时的实际工程困难。后来，人们描述了“静态”绝热逻辑族，但它们实际上不是完全绝热的，也不是完全静态的，而且速度要慢得多。在本文中，我们描述了一个新的逻辑族，静态2级绝热逻辑（S2LAL），据我们所知，这是第一个CMOS逻辑族，既完全静态，又真正完全绝热（模泄漏）。此外，我们认为S2LAL是这类电路中最快的（在全流水线顺序电路中），每个逻辑阶段的延迟为1个刻度（转换时间），最小时钟周期（启动间隔）为8个刻度。S2LAL需要提供8相的梯形功率时钟波形（加上恒定功率和接地参考）。我们认为，如果在合适的制造工艺中实施，旨在积极减少泄漏，S2LAL应该能够比目前已知的任何其他基于半导体的数字逻辑家族展示更高的能源效率。
To advance the energy efficiency of general digital computing far beyond the thermodynamic limits that apply to conventional digital circuits will require utilizing the principles of reversible computing. It has been known since the early 1990s that reversible computing based on adiabatic switching is possible in CMOS, although almost all the "adiabatic" CMOS logic families in the literature are not actually fully adiabatic, which limits their achievable energy savings. The first CMOS logic style achieving truly, fully adiabatic operation if leakage was negligible (CRL) was not fully static, which led to practical engineering difficulties in the presence of certain nonidealities. Later, "static" adiabatic logic families were described, but they were not actually fully adiabatic, or fully static, and were much slower.In this paper, we describe a new logic family, Static 2-Level Adiabatic Logic (S2LAL), which is, to our knowledge, the first CMOS logic family that is both fully static, and truly, fully adiabatic (modulo leakage). In addition, S2LAL is, we think, the fastest possible such family (among fully pipelined sequential circuits), having a latency per logic stage of one tick (transition time), and a minimum clock period (initiation interval) of 8 ticks. S2LAL requires 8 phases of a trapezoidal power-clock waveform (plus constant power and ground references) to be supplied. We argue that, if implemented in a suitable fabrication process designed to aggressively minimize leakage, S2LAL should be capable of demonstrating a greater level of energy efficiency than any other semiconductor-based digital logic family known today.