Skewed CMOS: noise-tolerant high-performance low-power static circuit family
Skewed CMOS: noise-tolerant high-performance low-power static circuit family
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偏斜 CMOS：耐噪声高性能低功耗静态电路系列
DOI：
10.1109/tvlsi.2002.800519
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发表时间：
2002
期刊：
影响因子：
--
通讯作者：
K. Roy
中科院分区：
文献类型：
--
作者：
A. Solomatnikov;D. Somasekhar;N. Sirisantana;K. Roy
本文提出了一种适用于低电压工作的高性能抗噪声静态电路系列，称为偏斜逻辑。与Domino逻辑相比，偏斜逻辑电路具有更好的可伸缩性，并且由于具有更好的噪声裕度，因此更适合于低电压应用。在延迟、功耗和动态噪声裕度方面，已经将倾斜逻辑和它的变体与Domino逻辑进行了比较。提出了一种倾斜CMOS流水线电路的设计方法。为了证明所提出的逻辑风格的适用性，使用歪斜逻辑电路设计了0.35 /spl mu/m 5.56 ns CMOS 16/spl倍/16位乘法器，并通过MOSIS制造。测量结果表明，由于时钟负载低，该倍增器仅消耗195 mW的功率。
In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, power, and dynamic noise margin. A design methodology for skewed CMOS pipelined circuits has been developed. To demonstrate the applicability of the proposed logic style, 0.35 /spl mu/m 5.56 ns CMOS 16/spl times/16 bit multipliers have been designed using skewed logic circuits and fabricated through MOSIS. Measurement results show that the multiplier only consumed a power of 195 mW due to its low clock load.