A Dual-Consistency Cache Coherence Protocol
A Dual-Consistency Cache Coherence Protocol
复制标题
双一致性缓存一致性协议
DOI：
10.1109/ipdps.2015.43
复制
发表时间：
2015
期刊：
影响因子：
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通讯作者：
A. Jimborean
中科院分区：
文献类型：
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作者：
Alberto Ros;A. Jimborean
弱内存一致性模型可以通过支持硬件和编译器优化来最大化系统性能，但是增加了编程复杂性，因为它们不符合程序员的直觉。设计一个具有直观记忆模型的高效系统是一个公开的挑战。本文提出了一种双一致性缓存一致性协议SPEL，它同时保证了硬件提供的最强内存一致性模型，并在性能和能耗方面取得了改进。该协议的设计利用了代码区域的编译时识别，可以在限制较少的情况下执行，从而优化了协议，而不会损害正确性。在这些区域之外，代码在更严格的协议下执行，该协议强制执行顺序一致性。与标准目录协议相比，我们发现64核芯片多处理器的性能平均提高了24%，能耗平均降低了32%。
Weak memory consistency models can maximize system performance by enabling hardware and compiler optimizations, but increase programming complexity since they do not match programmers' intuition. The design of an efficient system with an intuitive memory model is an open challenge. This paper proposes SPEL, a dual-consistency cache coherence protocol which simultaneously guarantees the strongest memory consistency model provided by the hardware and yields improvements in both performance and energy consumption. The design of the protocol exploits a compile-time identification of code regions which can be executed under a less restrictive, thus optimized protocol, without harming correctness. Outside these regions, code is executed under a more restrictive protocol which enforces sequential consistency. Compared to a standard directory protocol, we show improvements in performance of 24% and reductions in energy consumption of 32%, on average, for a 64-core chip multiprocessor.