A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing
A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing
复制标题
具有无分段和水平/垂直可访问性的低功耗和高面积 SRAM 核心架构，可实现超并行视频处理
DOI：
10.1093/ietele/e89-c.11.1629
复制
发表时间：
2006
期刊：
影响因子：
--
通讯作者：
M. Yoshimoto
中科院分区：
文献类型：
--
作者：
J. Miyakoshi;Y. Murachi;T. Ishihara;H. Kawaguchi;M. Yoshimoto
For super-parallel video processing, we proposed a power-and area-efficient SRAM core architecture with a segmentation-free access, which means accessibility to arbitrary consecutive pixels, and horizontal/vertical access. To achieve these flexible accesses, a spirally-connected local-wordline select signal and multi-selection scheme in word-lines are proposed, so that extra X-decoders in the conventional multi-division SRAM can be eliminated. Consequently, the proposed SRAM reduces a power and area by 57-60% and 60%, respectively, when it is applied to a 128 parallel architecture. The proposed 160-kbit SRAM with 16-read ports (2-read port SRAM with eight-parallel architecture) is implemented to a search window buffer for an H.264 motion estimation processor core which dissipates 800 μW for QCIF 15-fps in a 130-nm technology.
