Cost-Effective TSV Grouping for Yield Improvement of 3D-ICs
Cost-Effective TSV Grouping for Yield Improvement of 3D-ICs
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DOI：
10.1109/ats.2011.37
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发表时间：
2011-11
期刊：
影响因子：
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通讯作者：
Yi Zhao;S. Khursheed;B. Al-Hashimi
中科院分区：
文献类型：
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作者：
Yi Zhao;S. Khursheed;B. Al-Hashimi
三维集成电路（3D-IC）垂直堆叠多个硅管芯以减少总导线长度、功耗并允许异构技术的集成。硅通孔（TSV）作为层间的垂直连接，对3D集成设计提出了挑战。TSV缺陷可能发生在制造工艺和键合阶段，这会降低成品率并增加成本。最近的工作提出了采用冗余TSV来提高3D-IC的良率。本文提出了一种冗余TSV分组技术，将常规TSV和冗余TSV划分为组。对于每一组，使用一组多路复用器来选择远离有缺陷TSV的良好信号路径。我们研究分组比（一组中的常规到冗余TSV）对良率和硬件开销之间的权衡的影响。我们还展示了独立和聚类缺陷分布的影响下的概率模型的产量分析。仿真结果表明，对于给定数量的TSV和TSV故障率，仔细选择分组比导致实现100%的产量在最小的硬件成本（多路复用器和冗余TSV的数量）相比，不利用TSV分组比的设计。
Three-dimensional Integrated Circuits (3D-ICs) vertically stack multiple silicon dies to reduce overall wire length, power consumption, and allow integration of heterogeneous technologies. Through-silicon-vias (TSVs) which act as vertical links between layers pose challenges for 3D integration design. TSV defects can happen in fabrication process and bonding stage, which can reduce the yield and increase the cost. Recent work proposed the employment of redundant TSVs to improve the yield of 3D-ICs. This paper presents a redundant TSVs grouping technique, which partitions regular and redundant TSVs into groups. For each group, a set of multiplexers are used to select good signal paths away from defective TSVs. We investigate the impact of grouping ratio (regular-to-redundant TSVs in one group) on trade-off between yield and hardware overhead. We also show probabilistic models for yield analysis under the influence of independent and clustering defect distributions. Simulation results show that for a given number of TSVs and TSV failure rate, careful selection of grouping ratios lead to achieving 100% yield at minimal hardware cost (number of multiplexers and redundant TSVs) in comparison to a design that does not exploit TSV grouping ratios.